Information
I
2
C Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 17-15
17.4.3 Handshaking
The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices can hold
SCL low after completion of a 1-byte transfer (9 bits). In such cases, it halts the bus clock and forces the
master clock into wait states until the slave releases the SCL line.
17.4.4 Clock Control
The clock control block handles requests from the clock signal for transferring and controlling data for
multiple tasks.
A 9-cycle data transfer clock is requested for the following conditions:
• Master mode
— Transmit slave address after START condition
— Transmit slave address after repeated START condition
— Transmit data
— Receive data
• Slave mode
— Transmit data
— Receive data
— Receive slave address after START or repeated START condition
17.4.4.1 Clock Synchronization
Due to the wire AND logic on the SCL line, a high-to-low transition on the SCL line affects all devices
connected on the bus. The devices begin counting their low period when the master negates the SCL line.
After a device has negated SCL, it holds the SCL line low until the clock high state is reached. However,
the change of low-to-high in a device clock may not change the state of SCL if another device is still within
its low period. Therefore, SCL is held low by the device with the longest low period. Devices with shorter
low periods enter a high wait state during this time. When all devices concerned have counted off their low
periods, SCL is released and asserted. Then there is no difference between the devices’ clocks and the state
of SCL, and all the devices begin counting their high periods. The first device to complete its high period
negates SCL again.
17.4.4.2 Input Synchronization and Digital Filter
The following sections describes synchronization of the input signals and the filtering of SCL and SDA in
detail.
17.4.4.2.1 Input Signal Synchronization
The input synchronization block synchronizes the input SCL and SDA signals to the system clock and
detects transitions of these signals.