Information

I
2
C Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
17-14 Freescale Semiconductor
17.4.1.6 Address Compare—Implementation Details
The address compare block determines whether a slave has been properly addressed, either by its slave
address or by the general broadcast address (which addresses all slaves). The following address
comparisons are performed:
• Whether a broadcast message has been received, to update I2CSR
• Whether the module has been addressed as a slave, to update I2CSR and to generate an interrupt
• Whether the address transmitted by the current master matches the general broadcast address
17.4.2 Arbitration Procedure
The I
2
C interface is a true multiple-master bus. If two or more masters simultaneously try to control the
bus, each master’s clock synchronization procedure (including the I
2
C module) determines the bus
clock—the low period is equal to the longest clock-low period and the high is equal to the shortest one
among the masters. A bus master loses arbitration if it transmits a logic 1 on SDA while another master
transmits a logic 0. The losing masters immediately switch to slave-receive mode and stop driving the
SDA line. In this case, the transition from master to slave mode does not generate a STOP condition.
Meanwhile, the I
2
C unit sets I2CSR[MAL] to indicate the loss of arbitration and, as a slave, services the
transaction if it is directed to itself.
If the I
2
C module is enabled in the middle of an ongoing byte transfer, the interface behaves as follows:
• Slave mode—the I
2
C module ignores the current transfer on the bus and starts operating whenever
a subsequent START condition is detected.
• Master mode—the I
2
C module cannot tell whether the bus is busy; therefore, if a START condition
is initiated, the current bus cycle can be corrupted. This ultimately causes in the current bus master
to lose arbitration, after which bus operations return to normal.
17.4.2.1 Arbitration Control
The arbitration control block controls the arbitration procedure of the master mode. A loss of arbitration
occurs whenever the master detects a 0 on the external SDA line while attempting to drive a 1, tries to
generate a START or repeated START at an inappropriate time, or detects an unexpected STOP request on
the line.
In master mode, arbitration by the master is lost (and I2CSR[MAL] is set) under the following conditions:
• SDA samples low when the master drives high during an address or data-transmit cycle (transmit).
• SDA samples low when the master drives high during a data-receive cycle of the acknowledge
(ACK) bit (receive).
• A START condition is attempted when the bus is busy.
• A repeated START condition is requested in slave mode.
• A repeated START condition is attempted when the requesting device is not the bus owner
• Unexpected STOP condition detected
Note that the I
2
C module does not automatically retry a failed transfer attempt.