Information

I
2
C Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
17-10 Freescale Semiconductor
17.3.1.6 Digital Filter Sampling Rate Register (I2CDFSRR)
I2CDFSRR is shown in Figure 17-7.
Table 17-9 shows the I2CDFSRR field descriptions.
17.4 Functional Description
The I
2
C unit always performs as a slave receiver as a default, unless explicitly programmed to be a master
or slave transmitter. If boot sequencer mode is selected, the I
2
C interface performs as a slave receiver after
the boot sequence has completed.
17.4.1 Transaction Protocol
A standard I
2
C transfer consists of the following:
• START condition
• Slave target address transmission
• Data transfer
• STOP condition
Offset 0x0_3014 Access: Read/write
0x0_3114
012 7
R
—DFSR
W
Reset00010000
Figure 17-7. I
2
C Digital Filter Sampling Rate Register (I2CDFSRR)
Table 17-9. I2CDFSRR Field Descriptions
Bits Name Description
0–1 — Reserved, should be cleared
2–7 DFSR Digital filter sampling rate. To assist in filtering out signal noise, the sample rate is programmed. DFSR is used
to prescale the frequency at which the digital filter takes samples from the I
2
C bus. The resulting sampling
rate is calculated by dividing the platform frequency by the non-zero value of DFSR. If I2CDFSRR is cleared,
the I
2
C bus sample points default to the reset divisor 0x10.