Information

I
2
C Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 17-9
17.3.1.5 I
2
C Data Register (I2CDR)
The I2C data register is shown in Figure 17-6.
Table 17-8 shows the bit descriptions for I2CDR.
6 MIF Module interrupt. The MIF bit is set when an interrupt is pending, causing a processor interrupt request
(provided I2CCR[MIEN] is set).
0 No interrupt is pending. Can be cleared only by software.
1 Interrupt is pending. MIF is set when one of the following events occurs:
• One byte of data is transferred (set at the falling edge of the 9th clock).
• The value in I2CADR matches with the calling address in slave-receive mode.
• Arbitration is lost.
7 RXAK Received acknowledge. The value of SDAn during the reception of acknowledge bit of a bus cycle. If the
received acknowledge bit (RXAK) is low, it indicates that an acknowledge signal has been received after
the completion of eight bits of data transmission on the bus. If RXAK is high, it means no acknowledge
signal has been detected at the 9th clock.
0 Acknowledge received
1 No acknowledge received
Offset 0x0_3010 Access: Read/write
0x0_3110
0 7
R
DATA
W
Reset All zeros
Figure 17-6. I
2
C Data Register (I2CDR)
Table 17-8. I2CDR Field Descriptions
Bits Name Description
0–7 DATA Transmission starts when an address and the R/W bit are written to the data register and the I
2
C interface
performs as the master. A data transfer is initiated when data is written to the I2CDR. The most-significant bit
is sent first in both cases. In master receive mode, reading the data register allows the read to occur, but also
allows the I
2
C module to receive the next byte of data on the I
2
C interface. In slave mode, the same function
is available after it is addressed. Note that in both master receive and slave receive modes, the very first read
is always a dummy read.
Table 17-7. I2CSR Field Descriptions (continued)
Bits Name Description