Information

I
2
C Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
17-8 Freescale Semiconductor
17.3.1.4 I
2
C Status Register (I2CSR)
I2CSR is shown in Figure 17-5.
Table 17-7 describes the bit settings of the I2CSR.
Offset 0x0_300C Access: R/W
0x0_310C
01234567
R MCF MAAS MBB
MAL
BCSTM SRW
MIF
RXAK
W
Reset10000001
Figure 17-5. I
2
C Status Register (I2CSR)
Table 17-7. I2CSR Field Descriptions
Bits Name Description
0 MCF Data transfer. When one byte of data is transferred, the bit is cleared. It is set by the falling edge of the 9th
clock of a byte transfer.
0 Byte transfer in progress. MCF is cleared under the following conditions:
• When I2CDR is read in receive mode or when I2CDR is written in transmit mode.
• After a start sequence is recognized by the I
2
C controller in slave mode.
1 Byte transfer is completed
1 MAAS Addressed as a slave. When the value in I2CADR matches the calling address or when the calling address
is the broadcast address and broadcast mode is enabled (I2CCR[BCST] is set), this bit is set. The
processor is interrupted if I2CCR[MIEN] is set. Next, the processor must check the SRW bit and set
I2CCR[MTX] accordingly. Writing to the I2CCR automatically clears this bit.
0 Not addressed as a slave
1 Addressed as a slave
2 MBB Bus busy. Indicates the status of the bus. When a START condition is detected, MBB is set. If a STOP
condition is detected, it is cleared.
0I
2
C bus is idle
1I
2
C bus is busy
3 MAL Arbitration lost. Automatically set when the arbitration procedure is lost. Note that the device does not
automatically retry a failed transfer attempt.
0 Arbitration is not lost. Can only be cleared by software
1 Arbitration is lost
4 BCSTM Broadcast match. Writing to the I2CCR automatically clears this bit.
0 There has not been a broadcast match.
1 The calling address matches with the broadcast address and broadcast mode is enabled. This is also
set if this I
2
C drives an address of all 0s.
5 SRW Slave read/write. When MAAS is set, SRW indicates the value of the R/W command bit of the calling
address, which is sent from the master.
0 Slave receive, master writing to slave
1 Slave transmit, master reading from slave. This bit is valid only when both of the following conditions are
true:
• A complete transfer occurred and no other transfers have been initiated.
•The I
2
C interface is configured as a slave and has an address match.
By checking SRW, the processor can select slave transmit/receive mode according to the command of the
master.