Information

I
2
C Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 17-7
Table 17-6 describes the I2CCR bit settings.
.
Table 17-6. I2CCR Field Descriptions
Bits Name Description
0 MEN Module enable. Controls the software reset of the I
2
C module.
0 The module is reset and disabled. The interface is held in reset, but the registers can still be accessed.
1 The I
2
C module is enabled. MEN must be set before any other control register bits have any effect. All I
2
C
registers for slave receive or master START can be initialized before setting this bit.
1 MIEN Module interrupt enable
0 Interrupts from the I
2
C module are disabled. This does not clear any pending interrupt conditions.
1 Interrupts from the I
2
C module are enabled. An interrupt occurs provided I2CSR[MIF] is also set.
2 MSTA Master/slave mode START
0 On a transition to zero, a STOP condition is generated and the mode changes from master to slave.
Cleared without generating a STOP condition when the master loses arbitration.
1 When MSTA changes from zero to one, a START condition is generated on the bus and master mode is
selected.
3 MTX Transmit/receive mode select. Selects the direction of the master and slave transfers. When configured as a
slave, this bit should be set by software according to I2CSR[SRW]. In master mode, the bit should be set
according to the type of transfer required. Therefore, for address cycles, this bit will always high. MTX is
cleared when the master loses arbitration.
0 Receive mode
1 Transmit mode
4 TXAK Transfer acknowledge. Specifies the value driven onto the SDA line during acknowledge cycles for both
master and slave receivers. The value of this bit applies only when the I
2
C module is configured as a receiver,
not a transmitter. It also does not apply to address cycles; when the device is addressed as a slave, an
acknowledge is always sent.
0 An acknowledge signal (low value on SDA) is sent out to the bus at the 9th clock bit after receiving one
byte of data.
1 No acknowledge signal response (high value on SDA) is sent.
5 RSTA Repeated START. Note that this bit is not readable, which means if a read is performed to RSTA, a zero value
is returned.
0 No START condition is generated
1 Setting this bit always generates a repeated START condition on the bus, provides the device with the
current bus master. Attempting a repeated START at the wrong time (or if the bus is owned by another
master), results in loss of arbitration.
6 — Reserved, should be cleared
7 BCST Broadcast
0 Disables the broadcast accept capability
1 Enables the I
2
C to accept broadcast messages at address zero