Information

I
2
C Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 17-5
17.3.1 Register Descriptions
This section describes the I
2
C registers in detail. Note that reserved bits should always be written with the
value they return when read. That is, the register should be programmed by reading the value, modifying
appropriate fields, and writing back the value. The return value of the reserved fields should not be
assumed, even though the reserved fields return zero. This does not apply to the I
2
C data register (I2CDR).
17.3.1.1 I
2
C Address Register (I2CADR)
Figure 17-2 shows the I2CADR register, which contains the address to which the I
2
C interface responds
when addressed as a slave. Note that this is not the address that is sent on the bus during the address-calling
cycle when the I
2
C module is in master mode.
Table 17-4 describes the bit settings of I2CADR.
17.3.1.2 I
2
C Frequency Divider Register (I2CFDR)
Figure 17-3 shows the bits of the I
2
C frequency divider register.
Table 17-5 describes the bit settings of I2CFDR. It also maps I2CFDR[FDR] to the clock divider values.
Although it describes the ratio between the I
2
C controller internal clock and SCL, the default ratio of I
2
C
Offset 0x0_3000
0x0_3100
Access: Read/write
0 67
R
ADDR —
W
Reset All zeros
Figure 17-2. I
2
C Address Register (I2CADR)
Table 17-4. I2CADR Field Descriptions
Bits Name Description
0–6 ADDR Slave address. Contains the specific slave address that is used by the I
2
C interface. Note that the default
mode of the I
2
C interface is slave mode for an address match. Note that an address match is one of the
conditions that can cause I2CSR[MIF] to be set, signaling an interrupt pending condition.
7—Reserved
Offset 0x0_3004
0x0_3104
Access: Read/write
012 7
R
—FDR
W
Reset All zeros
Figure 17-3. I
2
C Frequency Divider Register (I2CFDR)