Information

I
2
C Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 17-3
HRESET is negated, the device may be initialized using boot sequence mode according to the
BOOTSEQ field in the reset configuration word. See Section 17.4.5, “Boot Sequencer Mode.”
Additionally, the following three I
2
C–specific states are defined for the I
2
C interface:
• START condition—This condition denotes the beginning of a new data transfer (each data transfer
contains several bytes of data) and awakens all slaves.
• Repeated START condition—A START condition that is generated without a STOP condition to
terminate the previous transfer.
• STOP condition—The master can terminate the transfer by generating a STOP condition to free
the bus.
17.2 External Signal Descriptions
The following sections give an overview of signals and provide detailed signal descriptions.
17.2.1 Signal Overview
The I
2
C interface uses the SDA and SCL signals, described in Table 17-1, for data transfer. Note that the
signal patterns driven on SDA represent address, data, or read/write information at different stages of the
protocol.
17.2.2 Detailed Signal Descriptions
SDA and SCL, described in Table 17-2, serve as a communication interconnect with other devices. All
devices connected to these signals must have open-drain or open-collector outputs. The logic AND
Table 17-1. I
2
C Interface Signal Descriptions
Signal Name Idle State I/O State Meaning
Serial Clock
(SCL1, SCL2)
High I When the I
2
C module is idle or acts as a slave, SCL defaults as an input. The unit uses SCL
to synchronize incoming data on SDA. The bus is assumed to be busy when SCL is detected
low.
O As a master, the I
2
C module drives SCL along with SDA when transmitting. As a slave, the
I
2
C module drives SCL negates for data pacing.
Serial Data
(SDA1, SDA2)
High I When the I
2
C module is idle or in a receiving mode, SDA defaults as an input. The unit
receives data from other
I
2
C devices on SDA. The bus is assumed to be busy when SDA is
detected low.
O When writing as a master or slave, the I
2
C module drives data on SDA synchronous to SCL.