Information

I
2
C Interface
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
17-2 Freescale Semiconductor
MPC8308 has two instances of I
2
C controllers. I
2
C controller 1 is used for boot sequencing and I
2
C
controller 2 is used for data communication.
17.1.1 Features
The I
2
C interface includes the following features:
• Two-wire interface
• Multiple-master operational
• Arbitration lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• START and STOP signal generation/detection
• Acknowledge bit generation/detection
• Bus busy detection
• Software-programmable clock frequency
• Software-selectable acknowledge bit
• On-chip filtering for spikes on the bus
17.1.2 Modes of Operation
The I
2
C unit on this device can operate in one of the following modes:
• Master mode.
The I
2
C initiates a transfer, generates clock signals, and terminates a transfer. It cannot use its own
slave address as a calling address. The I
2
C cannot be a master and a slave simultaneously.
• Slave mode.
The I
2
C is addressed by an I
2
C master. The module must be enabled before a START condition
from an I
2
C master is detected.
• Interrupt-driven byte-to-byte data transfer.
When successful slave addressing is achieved (and SCL returns to zero), the data transfer can
proceed on a byte-to-byte basis in the direction specified by the R/W
bit sent by the calling master.
Each byte of data must be followed by an acknowledge bit, which is signaled from the receiving
device. Several bytes can be transferred during a data transfer session.
• Boot sequencer mode.
I
2
C controller 1 supports boot sequencer mode. This mode can be used to initialize the
configuration registers in the device after the I
2
C module is initialized. Boot sequencer mode is
selected using the BOOTSEQ field in the reset configuration word high. Note that the hard-coded
reset configuration word high value is boot sequencer mode disabled.
• Reset configuration load.
In this mode, the I
2
C interface 1 loads the reset configuration words from an EEPROM at a specific
calling address while the rest of the device is in the reset state (HRESET
asserted). Once the reset
configuration words are latched inside the device, I
2
C is reset until HRESET is negated. After