Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 17-1
Chapter 17
I
2
C Interface
This chapter describes the inter-IC (IIC or I
2
C) bus interface implemented on this device.
17.1 Introduction
The inter-IC (IIC or I
2
C) bus is a two-wire—serial data (SDA) and serial clock (SCL)—bidirectional serial
bus that provides a simple, efficient method of data exchange between this device and other devices, such
as microcontrollers, EEPROMs, real-time clock devices, A/D converters, and LCDs. Figure 17-1 shows a
block diagram of an instance of I
2
C interface.
Figure 17-1. I
2
C Block Diagram
The two-wire I
2
C bus minimizes interconnections between devices. The synchronous, multiple-master I
2
C
bus allows the connection of additional devices to the bus for expansion and system development. The bus
includes collision detection and arbitration that prevent data corruption if two or more masters attempt to
control the bus simultaneously.
I2CADR I2CFDR I2CCR I2CSR I2CDR
Addr Decode Data Mux
Address
Compare
Input Sync
In/Out Data
Shift Register
Clock
Control
SDA
Address and Control Interrupt Data
arb_lost
and
Digital Filter
START/
STOP/
Repeated
Control
and
I2CDSRR
SCL
START
Arbitration
and