Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-178 Freescale Semiconductor
16.7.2 MAC: Half-Duplex Collision on FCS of Short Frame
Half-duplex collision on FCS of short frame may cause Tx lockup. In the half-duplex mode, if a collision
occurs in the FCS bytes of a short (less than 64 bytes) frame, then the Ethernet MAC may lock up and stop
transmitting data or control frames. Only a reset of the controller can restore proper operation once it is
locked up.
The following are the workarounds:
• Option 1: Set MACCFG2[PAD/CRC] = 1 that pads all short Tx frames to 64 bytes.
• Option 2: Use software-generated CRC (MACCFG2[PAD/CRC] = 0, MACCFG2[CRC EN] = 0,
and TxBD[TC] = 0).
Initialize RCTRL (Optional)
RCTRL[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize DMACTRL (Optional)
DMACTRL[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize (Empty) Transmit Descriptor ring and fill buffers with Data
Initialize TBASE0–TBASE7,
TBASE0–TBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]
Initialize (Empty) Receive Descriptor ring and fill with empty buffers
Initialize RBASE0–RBASE7,
RBASE0–RBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]
Enable Transmit Queues
Initialize TQUEUE
Enable Receive Queues
Initialize RQUEUE
Enable Rx and Tx,
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0101]
Table 16-154. RGMII Mode Register Initialization Steps (continued)