Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-177
Set up the MII Mgmt for a write cycle to the external PHY Control register (write the PHY address and Register address),
MIIMADD[0000_0000_0000_0000_0001_0001_0000_0000]
The control register (CR) is at offset address 0x00 from the external PHY address. (in this case 0x11)
Perform an MII Mgmt write cycle to the external PHY.
Write to MII Mgmt Control with 16-bit data intended for the external PHY Control register,
MIIMCON[0000_0000_0000_0000_0001_0010_0000_0000]
This enables the external PHY to restart Auto-Negotiations using the configuration set in the AN Advertisement register.
Check to see if MII Mgmt write is complete.
Read MII Mgmt Indicator register and check for Busy = 0,
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
This indicates that the write cycle was completed.
Check to see if PHY has completed Auto-Negotiation.
Set up the MII Mgmt for a read cycle to the PHY MII Mgmt register (write the PHY address and Register address),
MIIMADD[0000_0000_0000_0000_0000_0010_0000_0001]
The PHY Status register is at address 0x1 and in this case the PHY Address is 0x2.
Perform an MII Mgmt read cycle of Status Register.
Clear MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
(Uses the PHY address (2) and Register address (2) placed in MIIMADD register)
When MIIMIND[BUSY]=0,
read the MIIMSTAT register and check bit 10. (AN Done)
MIIMSTAT ---> [0000_0000_0000_0000_0000_0000_0010_0000]
Other information about the link is also returned. (Extend Status, No pre, Remote Fault, An Ability, Link status, extend Ability)
Perform an MII Mgmt read cycle of AN Expansion Register.
Setup MIIMADD[0000_0000_0000_0000_0001_0001_0000_0110]
Clear MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
(Uses the PHY address (0x11) and Register address (6) placed in MIIMADD register)
When MIIMIND[BUSY]=0,
read the MII Mgmt AN Expansion register and check bits 13 and 14. (NP Able and Page Rx’d)
MII Mgmt AN Expansion ---> [0000_0000_0000_0000_0000_0000_0000_0110]
Perform an MII Mgmt read cycle of AN Link Partner Base Page Ability Register. (Optional)
Setup MIIMADD[0000_0000_0000_0000_0001_0001_0000_0101]
Clear MIIMCOM[Read Cycle]
Set MIIMCOM[Read Cycle]
(Uses the PHY address (0x11) and Register address (5) placed in MIIMADD register)
When MIIMIND[BUSY]=0,
read the MII Mgmt AN Link Partner Base Page Ability register and check bits 9 and 10. (Half and Full Duplex)
MII Mgmt AN Link Partner Base Page Ability ---> [0000_0000_0000_0000_0000_000x_1x10_0000]
Clear IEVENT register,
IEVENT[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize IMASK (Optional)
IMASK[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize MACnADDR1/2 (Optional)
MACnADDR1/2[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize GADDRn (Optional)
GADDRn[0000_0000_0000_0000_0000_0000_0000_0000]
Table 16-154. RGMII Mode Register Initialization Steps (continued)