Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-176 Freescale Semiconductor
Table 16-153 describes the shared signals for the RGMII interface.
Table 16-154 describes the register initializations required to configure the eTSEC in RGMII mode.
Table 16-153. Shared RGMII Signals
eTSEC Signals I/O
No. of
Signals
GMII Signals I/O
No. of
Signals
Function
MDIO I/O 1 MDIO I/O 1 Management interface I/O
MDC O 1 MDC O 1 Management interface clock
Sum 2 Sum 2
Table 16-154. RGMII Mode Register Initialization Steps
Set Soft_Reset,
MACCFG1[1000_0000_0000_0000_0000_0000_0000_0000]
Clear Soft_Reset,
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize MACCFG2,
MACCFG2[0000_0000_0000_0000_0111_0010_0000_0101]
(I/F Mode = 2, Full Duplex = 1)
Initialize ECNTRL,
ECNTRL[0000_0000_0000_0000_0001_0000_0000_0000]
(This example has RGMII 10Mbps mode, Statistics Enable = 1)
Initialize MAC Station Address,
MACSTNADDR2[0110_0000_0000_0010_0000_0000_0000_0000]
to 02608C:876543, for example.
Initialize MAC Station Address,
MACSTNADDR1[0100_0011_0110_0101_1000_0111_1000_1100]
to 02608C:876543, for example.
Setup the MII Mgmt clock speed,
MIIMCFG[0000_0000_0000_0000_0000_0000_0000_0101]
Set source clock divide by 14, for example, to insure that TSEC_MDC clock speed is not greater than 2.5 MHz.
Read MII Mgmt Indicator register and check for Busy = 0,
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
This indicates that the eTSEC MII Mgmt bus is idle.
Set up the MII Mgmt for a write cycle to external the PHY AN Advertisement register (write the PHY address and Register
address),
MIIMADD[0000_0000_0000_0000_0001_0001_0000_0100]
The AN Advertisement register is at offset address 0x04 from the external PHY address. (in this case 0x11)
Perform an MII Mgmt write cycle to the external PHY.
Write to MII Mgmt Control with 16-bit data intended for the external PHY AN Advertisement register,
MIIMCON[0000_0000_0000_0000_u0uu_uuuu_uuuu_uuuu]
Where u must be selected by the user for proper system configuration.
Check to see if MII Mgmt write is complete.
Read MII Mgmt Indicator register and check for Busy = 0,
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
This indicates that the write cycle was completed.