Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-175
16.7.1.2 RGMII Interface Mode
Table 16-152 shows the signals configurations required for RGMII interface mode.
Initialize (Empty) Receive Descriptor ring and fill with empty buffers
Initialize RBASE0–RBASE7,
RBASE0–RBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]
Enable Transmit Queues
Initialize TQUEUE
Enable Receive Queues
Initialize RQUEUE
Enable Rx and Tx,
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0101]
Table 16-152. RGMII Interface Mode Signal Configuration
eTSEC Signals RGMII Interface
Frequency 125 [MHz]
Voltage 2.5 [V]
Signals I/O No. of Signals Signals I/O No. of Signals
GTX_CLK O 1 GTX_CLK O 1
GTX_CLK125/TX_CLK I 1 GTX_CLK125 I 1
not used
TxD[0] O 1 TxD[0]/TxD[4] O 1
TxD[1] O 1 TxD[1]/TxD[5] O 1
TxD[2] O 1 TxD[2]/TxD[6] O 1
TxD[3] O 1 TxD[3]/TxD[7] O 1
TX_EN O 1 TX_CTL (TX_EN/TX_ERR) O 1
TX_ER O 1 leave unconnected
RX_CLK I 1 RX_CLK I 1
RxD[0] I 1 RxD[0]/RxD[4] I 1
RxD[1] I 1 RxD[1]/RxD[5] I 1
RxD[2] I 1 RxD[2]/RxD[6] I 1
RxD[3] I 1 RxD[3]/RxD[7] I 1
RX_DV I 1 RX_CTL (RX_DV/RX_ERR) I 1
RX_ER I 1 not used
COL I 1 not used
CRS I 1 not used
Sum 17 Sum 13
Table 16-151. MII Mode Register Initialization Steps (continued)