Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-174 Freescale Semiconductor
Set up the MII Mgmt for a write cycle to the external PHY Extended PHY control register #1 to set up the interface mode selection.
MIIMADD[0000_0000_0000_0000_0000_0000_0001_0111]
Perform an MII Mgmt write cycle to the external PHY.
Write to MII Mgmt Control with 16-bit data intended for the external PHY register,
MIIMCON[0000_0000_0000_0000_0000_0000_0000_0000]
Check to see if MII Mgmt write is complete.
Read MII Mgmt Indicator register and check for Busy = 0,
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
This indicates that the write cycle was completed.
Set up the MII Mgmt for a write cycle to the external PHY Mode control register to set up the interface mode selection.
MIIMADD[0000_0000_0000_0000_0000_0000_0000_0000]
Perform an MII Mgmt write cycle to the external PHY.
Write to MII Mgmt Control with 16-bit data intended for the external PHY register,
MIIMCON[0000_0000_0000_0000_00uu_00uu_0u00_0000]
where u is user defined based on desired configuration.
Check to see if MII Mgmt write is complete
Read MII Mgmt Indicator register and check for Busy = 0,
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
This indicates that the write cycle was completed.
If auto-negotiation was enabled in the PHY, check to see if PHY has completed Auto-Negotiation.
Set up the MII Mgmt for a read cycle to PHY MII Mgmt register (write the PHY address and Register address),
MIIMADD[0000_0000_0000_0000_0000_0000_0000_0001]
The PHY Status register is at address 0x1 and in this case the PHY Address is 0x00.
Perform an MII Mgmt read cycle of Status Register.
Clear MIIMCOM[Read Cycle].
Set MIIMCOM[Read Cycle].
(Uses the PHY address (0) and Register address (1) placed in MIIMADD register),
When MIIMIND[BUSY]=0,
read the MIIMSTAT register and check bit 10 (AN Done and Link is up)
MIIMSTAT ---> [0000_0000_0000_0000_0000_0000_0010_0100]
Other information about the link is also returned.(Extend Status, No pre, Remote Fault, An Ability, Link status, extend Ability)
Check auto-negotiation attributes in the PHY as necessary.
Clear IEVENT register,
IEVENT[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize IMASK (Optional)
IMASK[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize MACnADDR1/2 (Optional)
MACnADDR1/2[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize GADDRn (Optional)
GADDRn[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize RCTRL (Optional)
RCTRL[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize DMACTRL (Optional)
DMACTRL[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize (Empty) Transmit Descriptor ring and fill buffers with Data
Initialize TBASE0–TBASE7,
TBASE0–TBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]
Table 16-151. MII Mode Register Initialization Steps (continued)