Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-173
Table 16-150 describes the shared signals of the MII interface.
Table 16-151 describes the register initializations required to configure the eTSEC in MII mode.
Table 16-150. Shared MII Signals
eTSEC Signals I/O
No. of
Signals
MII Signals I/O
No. of
Signals
Function
MDIO I/O 1 MDIO I/O 1 Management interface I/O
MDC O 1 MDC O 1 Management interface clock
Sum
2
Sum
2
Table 16-151. MII Mode Register Initialization Steps
Set Soft_Reset,
MACCFG1[1000_0000_0000_0000_0000_0000_0000_0000]
Clear Soft_Reset,
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize MACCFG2, for MII, half duplex operation.
Set I/F Mode bit,
MACCFG2[0000_0000_0000_0000_0111_0001_0000_0100]
(This example has Full Duplex = 0, Preamble count = 7, PAD/CRC append = 1)
Initialize ECNTRL,
ECNTRL[0000_0000_0000_0000_0001_0000_0000_0000]
(This example has Statistics Enable = 1)
Initialize MAC Station Address,
MACSTNADDR2[0110_0000_0000_0010_0000_0000_0000_0000]
Set station address to 02_60_8C_87_65_43, for example.
Initialize MAC Station Address,
MACSTNADDR1[0100_0011_0110_0101_1000_0111_1000_1100]
Set station address to 02_60_8C_87_65_43, for example.
Reset the management interface.
MIIMCFG[1000_0000_0000_0000_0000_0000_0000_0111]
Setup the MII Mgmt clock speed,
MIIMCFG[0000_0000_0000_0000_0000_0000_0000_0101]
set source clock divide by 14 for example to insure that MDC clock speed is not greater than 2.5 MHz
Read MII Mgmt Indicator register and check for Busy = 0,
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
This indicates that the eTSEC MII Mgmt bus is idle.
Set up the MII Mgmt for a write cycle to the external PHY Auxiliary Control and Status Register to configure the PHY through the
Management interface (overrides configuration signals of the PHY).
MIIMADD[0000_0000_0000_0000_0000_0000_0001_1100]
Perform an MII Mgmt write cycle to the external PHY
Writing to MII Mgmt Control with 16-bit data intended for the external PHY register,
MIIMCON[0000_0000_0000_0000_0000_0000_0000_0100]
Check to see if MII Mgmt write is complete
Read MII Mgmt Indicator register and check for Busy = 0,
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
This indicates that the write cycle was completed.