Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-170 Freescale Semiconductor
The RxBD definition is interpreted by eTSEC hardware as if RxBDs mapped to C data structures in the
manner illustrated by Figure 16-135.
typedef unsigned short uint_16; /* choose 16-bit native type */
typedef unsigned int uint_32; /* choose 32-bit native type */
typedef struct rxbd_struct {
uint_16 flags;
uint_16 length;
uint_32 bufptr;
} rxbd;
Figure 16-135. Mapping of RxBDs to a C Data Structure
Table 16-148 describes the fields of the RxBD.
Table 16-148. Receive Buffer Descriptor Field Descriptions
Offset Bits Name Description
0–1 0 E Empty, written by the eTSEC (when cleared) and by the user (when set).
0 The data buffer associated with this BD is filled with received data, or data reception is aborted due
to an error condition. The status and length fields have been updated as required.
1 The data buffer associated with this BD is empty, or reception is currently in progress.
1 RO1 Receive software ownership bit.
This field is reserved for use by software. This read/write bit is not modified by hardware, nor does its
value affect hardware.
2 W Wrap, written by user.
0 The next buffer descriptor is found in the consecutive location.
1 The next buffer descriptor is found at the location defined in RBASE.
3 I Interrupt, written by user.
0 No interrupt is generated after this buffer is serviced.
1 IEVENT[RXB] or IEVENT[RXF] are set after this buffer is serviced. This bit can cause an interrupt
if enabled (IMASK[RXBEN] or IMASK[RXFEN]). If the user wants to be interrupted only if RXF
occurs, then the user must disable RXB (IMASK[RXBEN] is cleared) and enable RXF
(IMASK[RXFEN] is set).
4 L Last in frame, written by the eTSEC.
0 The buffer is not the last in a frame.
1 The buffer is the last in a frame.
5 F First in frame, written by the eTSEC.
0 The buffer is not the first in a frame.
1 The buffer is the first in a frame.
6—Reserved
7 M Miss, written by the eTSEC. (This bit is valid only if the L-bit is set and eTSEC is in promiscuous mode.)
This bit is set by the eTSEC for frames that were accepted in promiscuous mode, but were flagged as
a “miss” by the internal address recognition; thus, while in promiscuous mode, the user can use the
M-bit to quickly determine whether the frame was destined to this station.
0 The frame was received because of an address recognition hit.
1 The frame was received because of promiscuous mode.