Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-169
16.6.7.3 Receive Buffer Descriptors (RxBD)
In the RxBD the user initializes the E, I, and W bits in the first word and the pointer in second word. If the
data buffer is used, the eTSEC modifies the E, L, F, M, BC, MC, LG, NO, CR, OV, and TR bits and writes
the length of the used portion of the buffer in the first word. The M, BC, MC, LG, NO, CR, OV, and TR
bits in the first word of the buffer descriptor are only modified by the eTSEC if the L (last BD in frame)
bit is set. The first word of the RxBD contains control and status bits. Its formats are detailed below.
The number of buffer descriptors in a ring is set using the W bit to indicate that the next buffer wraps back
to the beginning of the ring. See Section 16.5.3.5.5, “Maximum Frame Length Register (MAXFRM),” for
information on setting the size of the buffer ring.
Figure 16-134 defines the RxBD.
0–1 14 UN Underrun. Written by the eTSEC.
0 No underrun encountered (data was retrieved from external memory in time to send a complete
frame).
1 The Ethernet controller encountered a transmitter underrun condition while sending the
associated buffer. This could also have occurred in relation to a bus error causing
IEVENT[EBERR]. The eTSEC terminates the transmission and updates UN.
TOE TCP/IP off-load enable. Written by user. Valid only if set in the first BD of a frame.
0 No TCP/IP off-load acceleration is applied to the frame prior to transmission.
1 eTSEC looks for a TOE Frame Control Block preceding the frame, and applies TCP/IP off-load
acceleration as controlled by the FCB.
15 TR Truncation. Written by the eTSEC. Set in the last TxBD (TxBD[L] is set) when IEVENT[BABT]
occurs for a frame (a frame length greater than or equal to the value set in the maximum frame
length register is encountered, the HFE bit in the BD is cleared, and MACCFG2[Huge Frame] is
cleared). The frame is sent truncated.
2–3
0–15 Data
Length
Data length is the number of octets the eTSEC should transmit from this BD’s data buffer. It is never
modified by the eTSEC. This field must be greater than zero, as zero indicates a BD not ready.
4–7
0–31 TX Data
Buffer
Pointer
The transmit buffer pointer contains the address of the associated data buffer. The data buffer
pointer for the first BD of a TxPAL-enabled frame must be aligned on an 8-byte boundary. There are
no alignment restrictions for the data buffer pointers of the second or subsequent BDs of a
TxPAL-enabled frame, or for non-TxPAL frames.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Offset + 0 E RO1 W I L F 0 M BC MC LG NO SH CR OV TR
Offset + 2 DATA LENGTH
Offset + 4
RX DATA BUFFER POINTER
Offset + 6
Figure 16-134. Receive Buffer Descriptor
Table 16-147. Transmit Data Buffer Descriptor (TxBD) Field Descriptions (continued)
Offset Bits Name Description