Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-166 Freescale Semiconductor
The eTSEC clears the R bit in the first word of the BD after it finishes using the data buffer. The transfer
status bits are then updated. Additional transmit frame status can be found in statistic counters in the MIB
block.
Software must expect eTSEC to prefetch multiple TxBDs, and for TCP/IP checksumming an entire frame
must be read from memory before a checksum can be computed. Accordingly, the R bit of the first TxBD
in a frame must not be set until at least one entire frame can be fetched from this TxBD onwards. If eTSEC
prefetches TxBDs and fails to reach a last TxBD (with bit L set), it halts further transmission from the
current TxBD ring and report an underrun error as IEVENT[XFUN]; this indicates that an incomplete
frame was fetched, but remained unprocessed. The relevant TBPTR register points to the next unread
TxBD following the error.
Figure 16-133 defines the TxBD.
The TxBD definition is interpreted by eTSEC hardware as if TxBDs mapped to C data structures in the
manner shown in following code snippet.
typedef unsigned short uint_16; /* choose 16-bit native type */
typedef unsigned int uint_32; /* choose 32-bit native type */
typedef struct txbd_struct
{
uint_16 flags;
uint_16 length;
uint_32 bufptr;
} txbd;
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Offset + 0 R PAD/CRC W I L TC PRE/DEF 0 HFE/LC CF/RL RC TOE/UN TR
Offset + 2 DATA LENGTH
Offset + 4
TX DATA BUFFER POINTER
Offset + 6
Figure 16-133. Transmit Buffer Descriptor