Information

Reset, Clocking, and Initialization
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 4-3
4.2 Functional Description
This section describes the various ways to reset the device, the power-on reset configurations, and
clocking.
4.2.1 Reset Operations
The device has the following inputs to the reset logic:
• Power-on reset (PORESET)
• External hard reset (HRESET)
• Software watchdog reset
• System bus monitor reset
• Checkstop reset
• Software hard reset
All of these reset sources are fed into the reset controller and, depending on the source of the reset, different
actions are taken. The reset status register, described in Section 4.5.1.3, “Reset Status Register (RSR),”
indicates the last source to cause a reset.
4.2.1.1 Reset Causes
Table 4-3 describes reset causes.
TSECn_TX_CLK/
TSECn_GTX_CLK125
I Ethernet Transmit Clock. TSECn_TX_CLK is used in the MII mode. TSECn_GTX_CLK125 is
the 125-MHz clock used in the RGMII mode.
Timing Assertion/Negation—For timing information, see MPC8308 PowerQUICC II
Pro Processor Hardware Specification.
Reset State Always input.
Table 4-3. Reset Causes
Name Description
Power-on reset
(PORESET
)
Input signal. Asserting this signal initiates the power-on reset flow that resets the entire device
except RTC and configures various attributes of the device including its clock modes.
Hard reset (HRESET) A bidirectional I/O signal. The device can detect an external assertion of HRESET only while it is
not asserting hard reset. HRESET
is an open-drain signal.
Soft reset (SRESET) This is a high-priority interrupt to the e300 core that is generated by an external signal.
Software watchdog reset After the device watchdog counts to zero, a software watchdog reset is signaled. The enabled
software watchdog event then generates an internal hard reset sequence.
System bus monitor reset After the device CSB bus monitor reaches a timeout condition, a bus monitor reset is asserted.
The enabled bus monitor event then generates an internal hard reset sequence.
Table 4-2. External Clock Signals (continued)
Signal I/O Description