Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-160 Freescale Semiconductor
A representation of the PTP packet is shown in Figure 16-128.
Figure 16-128. PTP Packet Format
16.6.6.4.1 General Purpose Filer Rule
The eTSEC receive filer has been enhanced with the addition of a general-purpose event bit. This event
bit can be used in conjunction with filing table rules to identify 1588 packets and indicate these packets by
setting special timer status register bits (TMR_STAT). Additionally, 1588 packets can be easily identified
by upper-layer software using the filer to queue all PTP packets to one or more predefined virtual queues.
See Section 16.6.4.2.1, “Filing Rules” for further information.
16.6.6.5 Time-Stamp Insertion on Transmit Packets
Software has the option to write the time stamp of the transmitted frame to memory in the padding
alignment bytes (PAL) located between the TxFCB and the frame data. It is required that a minimum of
two TxBDs are used. The first points to the start of the 8 byte TxFCB. The second points to the start of
frame data. In memory, the TxFCB, and at least the first 16 bytes of the TxPAL must be adjacent, that is,
located in contiguous memory locations, as depicted in Figure 16-129.
The first TxBD[TOE] bit is set. When the TMR_CTRL[Record Time-stamp In PAL Enable] and
TxFCB[PTP] bits are set, the timestamp is written to memory location TxBD[Data Buffer Pointer]+16.
The second TxBD’s Data Length must either contain the full frame length, or a value greater than the
TxThreshold setting. Refer to Table 16-145. When time-stamps are inserted into the TxPAL, the
TMR_TXTSn_H/L and TMR_TXTSn_ID registers still function normally.
16.6.6.5.1 Interrupts
The TxPAL is updated with a time-stamp before closing the second TxBD. The TxBD[I] bit can be set for
the second TxBD frame to cause an interrupt (via IEVENT[TXF]) after the time-stamp has been written
to the TxPAL.
When time-stamps are inserted into the TxPAL, the TMR_TXTSn_H/L and TMR_TXTSn_ID registers
still function normally. Therefore, the 1588 interrupt can be triggered using the TMR_PEVENT register
bits TXP1, and TXP2.
Preamble SFD SRC DEST L/T CRCData
10101011 IP_H UDP_H PTP_Message
Time Stamp Point