Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-158 Freescale Semiconductor
16.6.6.2 Timer Logic Overview
The 1588 timer module can be partitioned into four different sub-modules as shown in Figure 16-126.
Figure 16-126. 1588 Timer Design Partition
16.6.6.3 Time-Stamp Insertion on the Received Packets
Every incoming packet’s 8-byte time stamp is inserted into the packet data buffer as padding alignment
bytes. Time-stamp insertion into the data buffer requires RCTRL[PAL] to be set to a value greater than or
equal to 8 and the control bit RCTRL[TS] bit to be set.
16.6.6.3.1 Timestamp Point
The required timestamp point, as specified in the IEEE 1588 Specification Sep-2004 (IEC 61588 First
Edition), is shown in Figure 16-127. From this, it is clear that the end of the SFD is the critical point in the
MII data stream.
Figure 16-127. Ethernet Sampling Points for 1588
The sample point coincides with the cycle after the SFD (Start of Frame Delimiter) detection by the MAC.
For received frames, this will be at least 4 bit times (MII) after the message timestamp point specified in
[1588]. For transmission, the eTSEC sample point precedes the sample point specified in [1588] by at least
4-bit times (MII). For a particular mode, the eTSEC sample point is a consistent number of bit times
1588 Timer
Clock
Time Stamp
Register Array
eTSEC
SFD Detection
Rx & Tx
Ethernet MAC
TMRCK TMRREG
SEL
TMRMAC
Tx PinsRx Pins
000 0 0 0 0 0 0 0 0 0 0
1 1 1 11111
Bit Time
Ethernet
Start of Frame
Delimiter
Preamble
Octet
First Octet
Following
Start of Frame
Message Timestamp
Point