Information

Reset, Clocking, and Initialization
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
4-2 Freescale Semiconductor
4.1.2 Clock Signals
In Table 4-2, some clock signals are specific to blocks within the device. Although some of their
functionality is described in Section 4.4, “Clocking,” they are defined in detail in their respective chapters.
See Figure 4-7 for the internal distribution of clocks in the device.
CFG_RESET_
SOURCE[0:3]
I Reset configuration word source selection. These signals are on device pins that have other functions
when the device is not in reset. They are sampled during the assertion of PORESET
to determine the
interface from which the device loads the reset configuration words.
State Meaning See Section 4.3.1.1, “Reset Configuration Word Source.”
Timing These signals are sampled during the assertion of PORESET after a stable clock is
supplied (PORESET
flow) and must be pulled high or low by external resistors as
long as HRESET is asserted.
Requirements During PORESET and HRESET flows, all other signal drivers connected to these
signals must be in the high-impedance state. For proper resistor values to pull reset
configuration signals high or low, see MPC8308 PowerQUICC II Pro Processor
Hardware Specification.
Reset State Input during power-on and hard reset flows. Functional signal after reset flow
completes.
SRESET
I This signal generates a high priority interrupt to the e300 core
State Meaning Asserted - An external agent has triggered a soft reset interrupt.
Negated - No soft reset interrupt.
Timing Assertion - Occur at any time, asynchronously to any clock
Negation - Must be asserted for at least 2 SYS_CLK_IN cycles.
Reset State High during power-on and hard reset flows.
Table 4-2. External Clock Signals
Signal I/O Description
SYS_CLK_IN I System clock. SYS_CLK_IN is the primary input clock.
Timing Assertion/Negation—For timing information, see MPC8308 PowerQUICC II
Pro Processor Hardware Specification.
Reset State Always input.
TSECn_RX_CLK I Ethernet Receive clock
Timing Assertion/Negation—For timing information, see MPC8308 PowerQUICC II
Pro Processor Hardware Specification.
Reset State Always input.
Table 4-1. System Control Signals (continued)
Signal I/O Description