Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-138 Freescale Semiconductor
16.6.2.12 Error-Handling Procedure
The eTSEC reports frame reception and transmission error conditions using the channel BDs, the error
counters, and the IEVENT register.
Transmission errors are described in Table 16-134.
Reception errors are described in Table 16-135.
Table 16-134. Transmission Errors
Error Response
Transmitter underrun Transmitter underrun can occur either after frame transmission has commenced, or in response to an
incomplete sequence of TxBDs. In the former case, the controller sends 32 bits that ensure a CRC
error, and terminates buffer transmission. In the latter case, the relevant transmit queue is halted. In
all cases, the eTSEC closes the buffer, sets TxBD[UN], IEVENT[XFUN], and IEVENT[TXE]. The
controller resumes transmission after TSTAT[THLT] is cleared (and DMACTRL[GTS] is cleared).
Retransmission
attempts limit expired
The controller terminates buffer transmission, sets TxBD[RL], closes the buffer, IEVENT[CRL], and
IEVENT[TXE]. Transmission resumes after TSTAT[THLT] is cleared (and DMACTRL[GTS] is cleared).
Late collision The controller terminates buffer transmission, sets TxBD[LC], closes the buffer, IEVENT[LC], and
IEVENT[TXE]. The controller resumes transmission after TSTAT[THLT] is cleared (and
DMACTRL[GTS] is cleared).
Memory read error A system bus error occurred during a DMA transaction. The controller sets IEVENT[EBERR], DMA
stops sending data to the FIFO which causes an underrun error, and therefore TxBD[UN] is set, but
IEVENT[XFUN] is not set. The TSTAT[THLT] is set. Transmits are continued once TSTAT[THLT] is
cleared.
Data parity error Data in the transmit FIFO was potentially corrupted. The controller sets IEVENT[DPE], but otherwise
continues transmission until halted explicitly.
Babbling transmit error A frame is transmitted which exceeds the MAC’s Maximum Frame Length and
MACCFG2[Huge Frame] is a 0. The controller sets IEVENT[BABT] and continues without interruption.
Table 16-135. Reception Errors
Error Description
Overrun error The Ethernet controller maintains an internal FIFO buffer for receiving data. If a receiver FIFO buffer
overrun occurs, the controller sets RxBD[OV], sets RxBD[L], closes the buffer, increments the
discarded frame counter (RDRP), and sets IEVENT[RXF], The receiver then enters hunt mode
(seeking start of a new frame).
Busy error A frame is received and discarded due to a lack of buffers. The controller sets IEVENT[BSY] and
increments the discarded frame counter (RDRP). In addition, the RSTAT[QHLTn] bit is set. RDRP
increments for each frame that is received while the receiver is halted due to a busy condition. The
halted queue resumes reception once the RSTAT[QHLTn] bit is cleared.
Filed frame to invalid
queue error
A frame is received and discarded as a result of the filer directing it to an RxBD ring that is currently
not enabled. The controller sets IEVENT[FIQ] and increments the discarded frame counter (RDRP).