Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-136 Freescale Semiconductor
16.6.2.9.1 Interrupt Coalescing
Interrupt coalescing offers the user the ability to contour the behavior of the eTSEC with regard to frame
interrupts. Separate but identical mechanisms exist for both transmitted frames and received frames. In
either case, frame interrupts require that software set the I-bit in RxBDs or TxBDs, and disable buffer
interrupts (IEVENT[RXB] or IEVENT[TXB]). Particular rings can remain free of interrupts by ensuring
that the I-bit is consistently cleared in all BDs. While interrupt coalescing is enabled, a transmit or receive
frame interrupt is raised either when a counter threshold-defined number of frames is received/transmitted
or the timer threshold-defined period of time has elapsed, whichever occurs first. Disabling and then
re-enabling interrupt coalescing forces reset of the coalescing timers and counters to reflect changes made
to the threshold registers.
16.6.2.9.2 Interrupt Coalescing By Frame Count Threshold
To avoid interrupt bandwidth congestion due to frequent, consecutive interrupts, the user may enable and
configure interrupt coalescing to deliberately group frame interrupts, reducing the total number of
interrupts raised. The number of frames received or transmitted prior to an interrupt being raised is
determined by the frame threshold field (ICFT) in the appropriate interrupt coalescing configuration
register (RXIC or TXIC). The frame threshold field may be assigned a value between 1 and 255. The
internal transmit or receive frame counter decrements from this initial value each time a frame is
transmitted or received. Upon reaching zero, an interrupt is raised, the appropriate threshold counter is
reset to the value in the ICFT field, and then eTSEC continues counting frames while the interrupt is active.
The appropriate threshold counter is also reset to the value in the ICFT field if an interrupt is raised subject
to the corresponding threshold timer.
16.6.2.9.3 Interrupt Coalescing By Timer Threshold
To avoid stale frame interrupts, the user may also assign a timer threshold, beyond which any frame
interrupts not yet raised are forced. The timer threshold fields of the receive and transmit interrupt
coalescing configuration registers (RXIC[ICTT] and TXIC[ICTT]) are defined in units equivalent to 64
interface clocks or system clocks, depending on the setting of the ICCS field in RXIC and TXIC.
After transmitting a frame, the transmit interrupt coalescing threshold time begins counting down from the
value in TXIC[ICTT]. An interrupt is raised when the counter reaches zero. In the event of graceful
transmit stop completion before the coalescing timer expires, the eTSEC issues two interrupts, the first for
GTS, the second for TXF (due to timer expiration of a pending event). To prevent the second interrupt from
affecting servicing of the GTS event, it is recommended that the user mask out the TXF event during
execution of the service routine. After receiving a frame, the receive interrupt coalescing threshold time
begins counting down from the value in RXIC[ICTT]. An interrupt is raised when the counter reaches
zero. In the event of graceful receive stop completion before the coalescing timer expires, the eTSEC
issues two interrupts, the first for GRS, the second for RXF (due to timer expiration of a pending event).
To prevent the second interrupt from affecting servicing of the GRS event, it is recommended that the user
mask out the RXF event during execution of the service routine.
The interrupt coalescing timer thresholds (transmit and receive, operating independently) may be values
ranging from 0x0001 to 0xFFFF. Table 16-133 specifies the range of possible timing thresholds subject to
timer clock source, the interface or system frequency, and the value of the RXIC[ICTT] or TXIC[ICTT]
field.