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Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-135
• Process the TxBDs to reuse them if the IEVENT[TXB, TXF or TXE] were set. Consult register
bits TSTAT[TXF0–TXF7] to determine which TxBD rings gave rise to the transmit interrupt in the
case of TXF. If the transmit speed is fast or the interrupt delay is long, more than one transmit buffer
may have been sent by the eTSEC; thus, it is important to check more than just one TxBD during
the interrupt handler. One common practice is to process all TxBDs in the interrupt handler until
one is found with R set.
• Obtain data from RxBD rings if IEVENT[RXC, RXB or RXF] is set. Consult register bits
RSTAT[RXF0–RXF7] to determine which RxBD rings gave rise to the receive interrupt in the case
of RXF. If the receive speed is fast or the interrupt delay is long, the eTSEC may have received
more than one RxBD; thus, it is important to check more than just one RxBD during interrupt
handling. Typically, all RxBDs in the interrupt handler are processed until one is found with E set.
Because the eTSEC pre-fetches BDs, the BD table must be big enough so that there is always
another empty BD to pre-fetch, otherwise a BSY error occurs.
• Clear any set halt or frame interrupt bits in TSTAT and RSTAT registers, or DMACTRL[GTS] and
DMACTRL[GRS] by writing 1s to these bits.
• Continue normal execution.
Table 16-131 describes the non-error transmit interrupts.
Table 16-132 shows the non-error receive interrupts.
Table 16-131. Non-Error Transmit Interrupts
Interrupt Description Action Taken by the eTSEC
GTSC Graceful transmit stop complete: transmitter is put into a pause state
after completion of the frame currently being transmitted.
None
TXC Transmit control: Instead of the next transmit frame, a control frame
was sent.
None
TXB Transmit buffer: A transmit buffer descriptor, that is not the last one in
the frame, was updated in one of the enabled TxBD rings.
Programmable ‘write with response’ TxBD
to memory before setting IEVENT[TXB].
TXF Transmit frame: A frame from an enabled TxBD ring was transmitted
and the last transmit buffer descriptor (TxBD) of that frame was
updated.
Programmable ‘write with response’ to
memory on the last TxBD before setting
IEVENT[TXF].
Table 16-132. Non-Error Receive Interrupts
Interrupt Description Action Taken by the eTSEC
GRSC Graceful receive stop complete: Receiver is put into a pause state after
completion of the frame currently being received.
None
RXC Receive control: A control frame was received. As soon as the
transmitter finishes sending the current frame, a pause operation is
performed.
None
RXB Receive buffer: A receive buffer descriptor, that is not the last one of
the frame, was updated in one of the enabled RxBD rings.
Programmable ‘write with response’ RxBD
to memory before setting IEVENT[RXB].
RXF Receive frame: A frame was received to an enabled RxBD ring and the
last receive buffer descriptor (RxBD) of that frame was updated.
Programmable ‘write with response’ to
memory on the last RxBD before setting
IEVENT[RXF].