Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
Freescale Semiconductor 16-121
• Section 16.6.5, “Lossless Flow Control”
• Section 16.6.7, “Buffer Descriptors”
16.6.1 Connecting to Physical Interfaces on Ethernet
This section describes how to connect the eTSEC to various interfaces: MII and RGMII. To avoid
confusion, all of the buses follow the bus conventions used in the IEEE 802.3 specification because the
PHYs follow the same conventions. (For instance, in the bus TSECn_TXD[3:0], bit 3 is the msb and bit 0
is the lsb). If a mode does not use all input signals available to a particular eTSEC, those inputs that are
not used must be pulled low on the board.
16.6.1.1 Media-Independent Interface (MII)
This section describes the media-independent interface (MII) intended to be used between the PHYs and
the eTSEC. Figure 16-117 depicts the basic components of the MII, including the signals required to
establish eTSEC module connection with a PHY.
Figure 16-117. eTSEC-MII Connection
An MII interface has 18 signals (including the MDC and MDIO signals), as defined by the IEEE 802.3u
standard, for connecting to an Ethernet PHY.
16.6.1.2 Reduced Gigabit Media-Independent Interface (RGMII)
This section describes the reduced gigabit media-independent interface (RGMII) intended to be used
between the PHYs and the GMII MAC. The RGMII is an alternative to the IEEE802.3u MII, the
Transmit Error (TSECn_TX_ER)
Transmit Data (TSECn_TXD[3:0])
Transmit Enable (TSECn_TX_EN)
Transmit Clock (TSECn_TX_CLK)
Collision Detect (TSECn_COL)
Receive Data (TSECn_RXD[3:0])
Receive Error (TSECn_RX_ER)
Receive Clock (TSECn_RX_CLK)
Receive Data Valid (TSECn_RX_DV)
Carrier Sense Output (TSECn_CRS)
Management Data I/O1 (MDIO)
eTSEC
10/100
PHY
Medium
1
The management signals (MDC and MDIO) are common to all of the Ethernet controllers’ connections
in the system, assuming that each PHY has a different management address.
Ethernet
Management Data Clock (MDC)
1