Information

Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-120 Freescale Semiconductor
The FIPER can get the following values: 80, 170, 260 .......
The three registers in eTSEC1 are shared for all eTSECs. Figure 16-115 describes the definition for the
TMR_FIPER register.
Table 16-123 describes the fields of the TMR_FIPER register.
16.5.3.10.14 External Trigger Stamp Register (TMR_ETTS1–2_H/L)
General purpose external trigger -stamp register (TMR_ETTSn_H/L). This register holds time at the
programmable edge of the external trigger. The registers in eTSEC1 are shared for all eTSECs. This
register is read only in normal operation. Figure 16-116 describes the definition for the TMR_ETTSn_H/L
register.
Table 16-124 describes the fields of the TMR_ETTSn_H/L register.
16.6 Functional Description
This section discusses the following:
• Section 16.6.1, “Connecting to Physical Interfaces on Ethernet”
• Section 16.6.2, “Gigabit Ethernet Controller Channel Operation”
• Section 16.6.3, “TCP/IP Off-Load”
• Section 16.6.4, “Quality of Service (QoS) Provision”
Offset eTSEC1:0x2_4E80+4*n Access: Read/Write
0 31
R
FIPER
W
Reset11111111111111111111111111111111
Figure 16-115. TMR_FIPERn Register Definition
Table 16-123. TMR_FIPER Register Field Descriptions
Bits Name Description
0–31 FIPER Fixed interval pulse period register. This field must be programmed to an integer multiple of
TMR_CTRL[TCLK_PERIOD] value to ensure a period pulse being generated correctly.
Offset eTSEC1:0x2_4EA0+8n Access: Read/Write
03132 63
R
ETTS_H ETTS_L
W
Reset All zeros
Figure 16-116. TMR_ETTS1-2_H/L Register Definition
Table 16-124. TMR_ETTS1-2_H Register Field Descriptions
Bits Name Description
0–63 ETTS_H/L Time stamp field at the programmable edge of the external trigger.