Information
Enhanced Three-Speed Ethernet Controllers
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
16-118 Freescale Semiconductor
Table 16-120 describes the fields of the TMR_PRSC register.
16.5.3.10.11 Timer Offset Register (TMROFF_H/L)
The timer offset register is used to provide current time by adding its value to the clock counter. Figure
16-113 describes the definition of the TMROFF_H/L register.
NOTE
All TMROFF_H registers in a device should be set to the same value, and
all TMROFF_L registers in a device should be set to the same value.
Otherwise, the precision time protocol may not work.
Table 16-121 describes the fields of the TMROFF_H/L register.
16.5.3.10.12 Alarm Time Comparator Register (TMR_ALARM1–2_H/L)
Alarm time comparator register (TMR_ALARMn_H/L). This register holds alarm time for comparison
with the current time counter. There are two of these registers for eTSEC1 which are shared amongst all
eTSECs. Figure 16-114 describes the definition for the TMR_ALARMn_H/L register.
Table 16-120. TMR_PRSC Register Field Descriptions
Bits Name Description
0–15 — Reserved
16–31 PRSC_OCK Output clock division/prescale factor. Output clock is generated by dividing the timer input clock by this
number. Programmed value in this field must be greater than 1. Any value less than 1 is treated as 2.
Offset eTSEC1:0x2_4E30 (H); 0x2_4E34 (L) Access: Read/Write
03132 63
R
TMROFF_H TMROFF_L
W
Reset All zeros
Figure 16-113. TMROFF_H/L Register Definition
Table 16-121. TMROFF_H/L Register Field Descriptions
Bits Name Description
0–63 TMROFF_H/L Offset value of the clock counter. Current time in is calculated by adding TMROFF_H/L with the
timer’s counter TMR_CNT_H/L register.
Offset eTSEC1:0x2_4E40+8n Access: Read/Write
0313263
R
ALARM_H ALARM_L
W
Reset 1111111111111111111111111111111 1 1 111111111111111111111111111111 1
Figure 16-114. TMR_ALARM1-2_H/L Register Definition