Information

MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 1
x Freescale Semiconductor
Figures
Figure
Number Title
Page
Number
11.4.9 System Control Register (SYSCTL)........................................................................ 11-22
11.4.10 Interrupt Status Register (IRQSTAT)....................................................................... 11-24
11.4.11 Interrupt Status Enable Register (IRQSTATEN) ..................................................... 11-28
11.4.12 Interrupt Signal Enable Register (IRQSIGEN) ....................................................... 11-31
11.4.13 Auto CMD12 Error Status Register (AUTOC12ERR)............................................ 11-33
11.4.14 Host Controller Capabilities (HOSTCAPBLT) ....................................................... 11-35
11.4.15 Watermark Level Register (WML).......................................................................... 11-36
11.4.16 Force Event Register (FEVT).................................................................................. 11-36
11.4.17 Host Controller Version Register (HOSTVER)....................................................... 11-38
11.4.18 DMA Control Register (DCR)................................................................................. 11-38
11.5 Functional Description................................................................................................. 11-38
11.5.1 Data Buffer .............................................................................................................. 11-39
11.5.2 DMA CSB Interface ................................................................................................ 11-41
11.5.3 SD Protocol Unit...................................................................................................... 11-42
11.5.4 Clock & Reset Manager........................................................................................... 11-44
11.5.5 Clock Generator....................................................................................................... 11-44
11.5.6 SDIO Card Interrupt ................................................................................................ 11-44
11.5.7 Card Insertion and Removal Detection.................................................................... 11-46
11.5.8 Power Management ................................................................................................. 11-46
11.6 Initialization/Application Information......................................................................... 11-47
11.6.1 Command Send and Response Receive Basic Operation........................................ 11-47
11.6.2 Card Identification Mode......................................................................................... 11-48
11.6.3 Card Access ............................................................................................................. 11-52
11.6.4 Switch Function....................................................................................................... 11-57
11.6.5 Commands for MMC/SD/SDIO.............................................................................. 11-60
11.7 Software Restrictions................................................................................................... 11-65
11.7.1 Initialization Active ................................................................................................. 11-65
11.7.2 Software Polling Procedure ..................................................................................... 11-65
11.7.3 Suspend Operation................................................................................................... 11-65
11.7.4 Data Port Access...................................................................................................... 11-65
11.7.5 Multi-block Read..................................................................................................... 11-65
Chapter 12
DMA Controller (DMAC)
12.1 Overview........................................................................................................................ 12-1
12.1.1 Features...................................................................................................................... 12-2
12.2 DMAC Memory Map/Register Definition .................................................................... 12-2
12.2.1 DMA Control Register (DMACR) ............................................................................ 12-3
12.3 DMA Error Status (DMAES) ........................................................................................ 12-6
12.3.1 DMA Enable Error Interrupt Register (DMAEEI).................................................... 12-8