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MPC8308 PowerQUICC II Pro

Processor Reference Manual

MPC8308RM

Rev. 1

09/2013

Summary of content (1176 pages)

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MPC8308 PowerQUICC II Pro Processor Reference Manual MPC8308RM Rev.
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How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein.
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Contents Paragraph Number Title Page Number About This Book Audience ...................................................................................................................... lvii Organization................................................................................................................. lvii Suggested Reading........................................................................................................ lix General Information........................................
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Figures Figure Number Title Page Number Chapter 3 Memory Map 3.1 3.2 3.3 Internal Memory-Mapped Registers ................................................................................ 3-1 Accessing IMMR Memory from the Local Processor..................................................... 3-1 IMMR Address Map ........................................................................................................ 3-1 Chapter 4 Reset, Clocking, and Initialization 4.1 4.1.1 4.1.2 4.2 4.2.1 4.2.2 4.2.3 4.
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Figures Figure Number 5.1.9 5.1.10 5.1.11 5.2 5.2.1 5.2.2 5.3 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.4.8 5.4.9 5.5 5.5.1 5.5.2 5.5.3 5.5.4 5.5.5 5.5.6 5.5.7 5.6 5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 5.6.6 5.6.7 5.7 Title Page Number Inbound Address Translation and Mapping Windows .............................................. 5-14 Internal Memory Map................................................................................................
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Figures Figure Number 5.7.1 5.7.2 5.7.3 Title Page Number External Signal Description ....................................................................................... 5-70 PMC Memory Map/Register Definition .................................................................... 5-70 Functional Description............................................................................................... 5-71 Chapter 6 Arbiter and Bus Monitor 6.1 6.1.1 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.
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Figures Figure Number 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 7.4.8 7.5 Title Page Number Instruction Set and Addressing Modes ...................................................................... 7-26 Cache Implementation ............................................................................................... 7-29 Interrupt Model .......................................................................................................... 7-31 Memory Management...........................................
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Figures Figure Number 8.5.21 8.5.22 8.5.23 8.6 8.6.1 8.6.2 8.6.3 8.6.4 8.6.5 8.6.6 8.6.7 8.6.8 8.6.9 8.7 8.7.1 8.7.2 Title Page Number System Error Force Register (SERFR)...................................................................... 8-29 System Critical Interrupt Vector Register (SCVCR) ................................................. 8-30 System Management Interrupt Vector Register (SMVCR) ....................................... 8-30 Functional Description.......................................
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Figures Figure Number 9.6 9.6.1 Title Page Number Initialization/Application Information ........................................................................... 9-60 DDR SDRAM Initialization Sequence ...................................................................... 9-62 Chapter 10 Enhanced Local Bus Controller 10.1 10.1.1 10.1.2 10.1.3 10.2 10.3 10.3.1 10.4 10.4.1 10.4.2 10.4.3 10.4.4 10.5 10.5.1 10.5.2 10.5.3 10.5.4 10.5.5 Introduction..........................................................
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Figures Figure Number 11.4.9 11.4.10 11.4.11 11.4.12 11.4.13 11.4.14 11.4.15 11.4.16 11.4.17 11.4.18 11.5 11.5.1 11.5.2 11.5.3 11.5.4 11.5.5 11.5.6 11.5.7 11.5.8 11.6 11.6.1 11.6.2 11.6.3 11.6.4 11.6.5 11.7 11.7.1 11.7.2 11.7.3 11.7.4 11.7.5 Title Page Number System Control Register (SYSCTL)........................................................................ 11-22 Interrupt Status Register (IRQSTAT).......................................................................
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Figures Figure Number 12.3.2 12.3.3 12.3.4 12.3.5 12.3.6 12.3.7 12.3.8 12.3.9 12.3.10 12.3.11 12.3.12 12.4 12.4.1 12.4.2 12.5 12.5.1 12.5.2 12.6 12.6.1 12.6.2 12.7 12.7.1 12.7.2 12.7.3 12.8 12.9 12.9.1 12.9.2 Title Page Number DMA Set Enable Error Interrupt (DMASEEI) .......................................................... 12-9 DMA Clear Enable Error Interrupt (DMACEEI) ...................................................... 12-9 DMA Clear Interrupt Request (DMACINT) ....................................
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Figures Figure Number 13.4 13.4.1 13.4.2 13.4.3 13.4.4 13.5 13.5.1 13.5.2 13.5.3 13.5.4 13.5.5 13.5.6 13.5.7 13.6 13.6.1 13.6.2 13.6.3 13.6.4 13.6.5 13.6.6 13.6.7 13.6.8 13.6.9 13.6.10 13.6.11 13.6.12 13.6.13 13.6.14 13.7 13.7.1 13.7.2 13.8 13.8.1 13.8.2 13.8.3 13.8.4 13.8.5 13.8.6 13.9 13.9.1 13.9.2 Title Page Number Functional Description................................................................................................. 13-44 System Interface ..............................................
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Figures Figure Number 13.9.3 13.9.4 13.9.5 13.9.6 13.10 Title Page Number Non-Zero Fields the Register File ......................................................................... 13-154 SOF Interrupt ......................................................................................................... 13-154 Embedded Design .................................................................................................. 13-154 Miscellaneous Variations from EHCI ....................................
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Figures Figure Number 14.6.2 14.6.3 14.6.4 14.6.5 14.7 14.7.1 14.8 14.8.1 14.8.2 14.8.3 14.8.4 Title Page Number Interrupts............................................................................................................... 14-122 Mailbox.................................................................................................................. 14-124 Power Management ............................................................................................... 14-126 Hot Reset.........
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Figures Figure Number 16.5.2 16.5.3 16.6 16.6.1 16.6.2 16.6.3 16.6.4 16.6.5 16.6.6 16.6.7 16.7 16.7.1 16.7.2 Title Page Number Detailed Memory Map............................................................................................. 16-10 Memory-Mapped Register Descriptions.................................................................. 16-21 Functional Description...............................................................................................
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Figures Figure Number Title Page Number Chapter 18 DUART 18.1 18.1.1 18.1.2 18.2 18.2.1 18.2.2 18.3 18.3.1 18.4 18.4.1 18.4.2 18.4.3 18.4.4 18.4.5 18.5 Overview........................................................................................................................ 18-1 Features...................................................................................................................... 18-2 Modes of Operation .......................................................................
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Figures Figure Number 20.3 Title Page Number JTAG Registers and Scan Chains .................................................................................. 20-3 Chapter 21 General Purpose I/O (GPIO) 21.1 21.1.1 21.1.2 21.2 21.2.1 21.3 21.3.1 21.3.2 21.3.3 21.3.4 21.3.5 21.3.6 Introduction.................................................................................................................... 21-1 Overview.....................................................................................
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Figures Figure Number A.21 A.22 A.23 Title Page Number SerDes PHY .................................................................................................................. A-31 Enhanced Secure Digital Host Controller (eSDHC)..................................................... A-32 Universal Serial Bus (USB) Interface........................................................................... A-32 Appendix B Revision History MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev.
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Figures Figure Number Title Page Number Figures 1-1 1-2 1-3 2-1 2-2 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 MPC8308 Block Diagram....................................................................................................... 1-1 MPC8308 Integrated e300c3 Core Block Diagram ................................................................ 1-9 USB Controllers Port Configuration....................
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Figures Figure Number 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28 5-29 5-30 5-31 5-32 5-33 5-34 5-35 5-36 5-37 5-38 5-39 5-40 5-41 5-42 5-43 5-44 5-45 5-46 5-47 5-48 5-49 5-50 5-51 5-52 5-53 5-54 6-1 6-2 6-3 6-4 Title Page Number PCI Express Controller Registers (PECR1).......................................................................... 5-29 eSDHC Control Register (SDHCCR) ...................................................................................
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Figures Figure Number 6-5 6-6 6-7 6-8 6-9 6-10 6-11 7-1 7-2 7-3 7-4 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 8-14 8-15 8-16 8-17 8-18 8-19 8-20 8-21 8-22 8-23 8-24 8-25 8-26 8-27 8-28 8-29 8-30 Title Page Number Arbiter Interrupt Definition Register (AIDR) ......................................................................... 6-7 Arbiter Mask Register (AMR) ................................................................................................
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Figures Figure Number 8-31 8-32 8-33 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 9-15 9-16 9-17 9-18 9-19 9-20 9-21 9-22 9-23 9-24 9-25 9-26 9-27 9-28 9-29 9-30 9-31 9-32 9-33 9-34 9-35 9-36 9-37 9-38 Title Page Number Message Shared Interrupt Mask Register (MSIMR) ............................................................ 8-41 Message Shared Interrupt Status Register (MSISR).............................................................
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Figures Figure Number 9-39 9-40 9-41 9-42 9-43 9-44 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-31 10-32 10-33 10-34 10-35 Title Page Number Registered DDR SDRAM DIMM Burst Write Timing ........................................................ 9-52 Write Timing Adjustments Example for Write Latency = 1.................................................
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Figures Figure Number 10-36 10-37 10-38 10-39 10-40 10-41 10-42 10-43 10-44 10-45 10-46 10-47 10-48 10-49 10-50 10-51 10-52 10-53 10-54 10-55 10-56 10-57 10-58 10-59 10-60 10-61 10-62 10-63 10-64 Title Page Number GPCM Basic Write Timing (XACS = 0, ACS = 00, CSNT = 1, SCY = 1, TRLX = 0, CLKDIV = 2, 4, 8)..............
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Figures Figure Number 10-65 10-66 10-67 10-68 10-69 10-70 10-71 10-72 10-73 10-74 10-75 10-76 10-77 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 11-16 11-17 11-18 11-19 11-20 11-21 11-22 11-23 11-24 11-25 11-26 11-27 12-1 Title Page Number LCSn Signal Selection ........................................................................................................ 10-78 LBS Signal Selection ...............................................................................
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Figures Figure Number 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 12-11 12-12 12-13 12-14 12-15 12-16 12-17 12-18 12-19 12-20 12-21 12-22 12-23 12-24 12-25 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 13-10 13-11 13-12 13-13 13-14 13-15 13-16 13-17 Title Page Number DMA Control Register (DMACR) ....................................................................................... 12-4 DMA Error Status Register (DMAES) .................................................................................
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Figures Figure Number 13-18 13-19 13-20 13-21 13-22 13-23 13-24 13-25 13-26 13-27 13-28 13-29 13-30 13-31 13-32 13-33 13-34 13-35 13-36 13-37 13-38 13-39 13-40 13-41 13-42 13-43 13-44 13-45 13-46 13-47 13-48 13-49 13-50 13-51 13-52 13-53 13-54 13-55 13-56 13-57 13-58 Title Page Number ULPI Register Access (ULPI VIEWPORT) ....................................................................... 13-23 Configure Flag Register (CONFIGFLAG) .......................................................................
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Figures Figure Number 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-72 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 14-13 14-14 14-15 14-16 14-17 14-18 14-19 14-20 14-21 14-22 14-23 14-24 14-25 14-26 14-27 Title Page Number Split Transaction State Machine for Isochronous ..............................................................13-111 Endpoint Queue Head Organization .................................................................................
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Figures Figure Number 14-28 14-29 14-30 14-31 14-32 14-33 14-34 14-35 14-36 14-37 14-38 14-39 14-40 14-41 14-42 14-43 14-44 14-45 14-46 14-47 14-48 14-49 14-50 14-51 14-52 14-53 14-54 14-55 14-56 14-57 14-58 14-59 14-60 14-61 14-62 14-63 14-64 14-65 14-66 14-67 14-68 Title Page Number PCI Express Secondary Status Register.............................................................................. 14-30 PCI Express Memory Base Register ....................................................................
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Figures Figure Number 14-69 14-70 14-71 14-72 14-73 14-74 14-75 14-76 14-77 14-78 14-79 14-80 14-81 14-82 14-83 14-84 14-85 14-86 14-87 14-88 14-89 14-90 14-91 14-92 14-93 14-94 14-95 14-96 14-97 14-98 14-99 14-100 14-101 14-102 14-103 14-104 14-105 14-106 14-107 14-108 14-109 Title Page Number PCI Express Uncorrectable Error Severity Register ........................................................... 14-55 PCI Express Correctable Error Status Register....................................................
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Figures Figure Number 14-110 14-111 14-112 14-113 14-114 14-115 14-116 14-117 14-118 14-119 14-120 14-121 14-122 14-123 14-124 14-125 14-126 14-127 14-128 14-129 14-130 14-131 14-132 14-133 14-134 14-135 14-136 14-137 14-138 14-139 14-140 14-141 14-142 Title Page Number PCI Express Inbound Mailbox Control Register (PEX_IMBCR) ...................................... 14-89 PCI Express Inbound Mailbox Data Register (PEX_IMBDR)...........................................
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Figures Figure Number 14-143 14-144 15-1 15-2 15-3 15-4 15-5 15-6 15-7 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 16-10 16-11 16-12 16-13 16-14 16-15 16-16 16-17 16-18 16-19 16-20 16-21 16-22 16-23 16-24 16-25 16-26 16-27 16-28 16-29 16-30 16-31 16-32 Title Page Number n-Way Chain Descriptor Organization in Host Memory .................................................. 14-132 Block Descriptor Organization in Host Memory ..............................................................
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Figures Figure Number 16-33 16-34 16-35 16-36 16-37 16-38 16-39 16-40 16-41 16-42 16-43 16-44 16-45 16-46 16-47 16-48 16-49 16-50 16-51 16-52 16-53 16-54 16-55 16-56 16-57 16-58 16-59 16-60 16-61 16-62 16-63 16-64 16-65 16-66 16-67 16-68 16-69 16-70 16-71 16-72 16-73 Title Page Number RBASE Register Definition ................................................................................................ 16-60 TMR_RXTS_H/L Register Definition..............................................................
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Figures Figure Number 16-74 16-75 16-76 16-77 16-78 16-79 16-80 16-81 16-82 16-83 16-84 16-85 16-86 16-87 16-88 16-89 16-90 16-91 16-92 16-93 16-94 16-95 16-96 16-97 16-98 16-99 16-100 16-101 16-102 16-103 16-104 16-105 16-106 16-107 16-108 16-109 16-110 16-111 16-112 16-113 16-114 Title Page Number Receive Dropped Packet Counter Register Definition ....................................................... 16-89 Transmit Byte Counter Register Definition .....................................................
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Figures Figure Number 16-115 16-116 16-117 16-118 16-119 16-120 16-121 16-122 16-123 16-124 16-125 16-126 16-127 16-128 16-129 16-130 16-131 16-132 16-133 16-134 16-135 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 17-10 17-11 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 Title Page Number TMR_FIPERn Register Definition ................................................................................... 16-120 TMR_ETTS1-2_H/L Register Definition...............................................................
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Figures Figure Number 18-10 18-11 18-12 18-13 18-14 18-15 19-1 19-2 19-3 19-4 19-5 19-6 19-7 19-8 19-9 19-10 19-11 19-12 19-13 19-14 19-15 20-1 21-1 21-2 21-3 21-4 21-5 21-6 21-7 Title Page Number Modem Control Register (UMCR1 and UMCR2).............................................................. 18-12 Line Status Register (ULSR1 and ULSR2) ........................................................................ 18-13 Scratch Register (USCR) .............................................................
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Tables Table Number Title Page Number Tables 1 2-1 2-2 3-1 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-32 4-33 5-1 Acronyms and Abbreviated Terms........................................................................................... lxi MPC8308 Signal Reference by Functional Block .................................................................. 2-3 Output Signal States During System Reset......
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Tables Table Number 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28 5-29 5-30 5-31 5-32 5-33 5-34 5-35 5-36 5-37 5-38 5-39 5-40 5-41 5-42 Title Page Number Local Access Windows Example............................................................................................ 5-2 Format of Window Definitions ...............................................................................................
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Tables Table Number 5-43 5-44 5-45 5-46 5-47 5-48 5-49 5-50 5-51 5-52 5-53 5-54 5-55 5-56 5-57 5-58 5-59 5-60 5-61 5-62 5-63 5-64 5-65 5-66 5-67 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 7-1 7-2 7-3 Title Page Number RTEVR Bit Settings .............................................................................................................. 5-44 RTALR Bit Settings ..............................................................................................................
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Tables Table Number 7-4 7-5 7-6 7-7 7-8 7-9 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 8-14 8-15 8-16 8-17 8-18 8-19 8-20 8-21 8-22 8-23 8-24 8-25 8-26 8-27 8-28 8-29 8-30 8-31 8-32 8-33 8-34 8-35 Title Page Number Using HID0[ECLK] and HID0[SBCLK] to Configure clk_out ........................................... 7-24 HID1 Bit Descriptions .......................................................................................................... 7-25 e300HID2 Bit Descriptions...................
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Tables Table Number 8-36 8-37 8-38 8-39 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 9-15 9-16 9-17 9-18 9-19 9-20 9-21 9-22 9-23 9-24 9-25 9-26 9-27 9-28 9-29 9-30 9-31 9-32 9-33 9-34 9-35 9-36 9-37 Title Page Number MSIRs Field Descriptions ..................................................................................................... 8-41 MSIMR Field Descriptions ...................................................................................................
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Tables Table Number 9-38 9-39 9-40 9-41 9-42 9-43 9-44 9-45 9-46 9-47 9-48 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 Title Page Number DDR2 Address Multiplexing for 32-Bit Data Bus with Interleaving and Partial Array Self Refresh Disabled ..............................................................................................................
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Tables Table Number 10-29 10-30 10-31 10-32 10-33 10-34 10-35 10-36 10-37 10-38 10-39 10-40 10-41 10-42 10-43 10-44 10-45 10-46 10-47 10-48 10-49 10-50 10-51 10-52 10-53 10-54 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 Title Page Number FPAR Field Descriptions, Large Page Device (ORx[PGS] = 1)......................................... 10-37 FBCR Field Descriptions ....................................................................................................
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Tables Table Number 11-16 11-17 11-18 11-19 11-20 11-21 11-22 11-23 11-24 11-25 11-26 11-27 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 12-11 12-12 12-13 12-14 12-15 12-16 12-17 12-18 12-19 12-20 12-21 12-22 12-23 13-1 13-2 13-3 13-4 13-5 Title Page Number Relation Between Data Timeout Error and Transfer Complete Status ............................... 11-28 Relation Between Command CRC Error and Command Timeout Error............................ 11-28 IRQSTATEN Field Descriptions...................
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Tables Table Number 13-6 13-7 13-8 13-9 13-10 13-11 13-12 13-13 13-14 13-15 13-16 13-17 13-18 13-19 13-20 13-21 13-22 13-23 13-24 13-25 13-26 13-27 13-28 13-29 13-30 13-31 13-32 13-33 13-34 13-35 13-36 13-37 13-38 13-39 13-40 13-41 13-42 13-43 13-44 13-45 13-46 Title Page Number HCSPARAMS Register Field Descriptions .......................................................................... 13-7 HCCPARAMS Register Field Descriptions..........................................................................
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Tables Table Number 13-47 13-48 13-49 13-50 13-51 13-52 13-53 13-54 13-55 13-56 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-72 13-73 13-74 13-75 13-76 13-77 13-78 13-79 13-80 13-81 13-82 13-83 13-84 13-85 13-86 13-87 Title Page Number Endpoint and Transaction Translator Characteristics ......................................................... 13-53 Microframe Schedule Control..................................................................................
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Tables Table Number 13-88 13-89 13-90 13-91 13-92 13-93 13-94 13-95 13-96 13-97 13-98 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 14-13 14-14 14-15 14-16 14-17 14-18 14-19 14-20 14-21 14-22 14-23 14-24 14-25 14-26 14-27 14-28 14-29 14-30 Title Page Number Interrupt/Bulk Endpoint Bus Response Matrix................................................................. 13-138 Control Endpoint Bus Response Matrix ...........................................................................
PAGE 48
Tables Table Number 14-31 14-32 14-33 14-34 14-35 14-36 14-37 14-38 14-39 14-40 14-41 14-42 14-43 14-44 14-45 14-46 14-47 14-48 14-49 14-50 14-51 14-52 14-53 14-54 14-55 14-56 14-57 14-58 14-59 14-60 14-61 14-62 14-63 14-64 14-65 14-66 14-67 14-68 14-69 14-70 14-71 Title Page Number PCI Express Prefetchable Memory Limit Register Fields Description .............................. 14-32 PCI Express Prefetchable Base Upper 32-Bit Register Fields Description ........................
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Tables Table Number 14-72 14-73 14-74 14-75 14-76 14-77 14-78 14-79 14-80 14-81 14-82 14-83 14-84 14-85 14-86 14-87 14-88 14-89 14-90 14-91 14-92 14-93 14-94 14-95 14-96 14-97 14-98 14-99 14-100 14-101 14-102 14-103 14-104 14-105 14-106 14-107 14-108 14-109 14-110 14-111 14-112 Title Page Number PCI Express Root Error Status Register Fields Description ............................................... 14-61 PCI Express Error Source Identification Register Fields Description ................................
PAGE 50
Tables Table Number 14-113 14-114 14-115 14-116 14-117 14-118 14-119 14-120 14-121 14-122 14-123 14-124 14-125 14-126 14-127 14-128 14-129 14-130 14-131 14-132 14-133 14-134 14-135 14-136 14-137 14-138 14-139 14-140 14-141 14-142 14-143 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 16-1 16-2 Title Page Number PEX_HIPIVR Register Fields Description ......................................................................... 14-93 PEX_HWDIVR Register Fields Description...............................................
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Tables Table Number 16-3 16-4 16-5 16-6 16-7 16-8 16-9 16-10 16-11 16-12 16-13 16-14 16-15 16-16 16-17 16-18 16-19 16-20 16-21 16-22 16-23 16-24 16-25 16-26 16-27 16-28 16-29 16-30 16-31 16-32 16-33 16-34 16-35 16-36 16-37 16-38 16-39 16-40 16-41 16-42 16-43 Title Page Number Module Memory Map Summary......................................................................................... 16-10 Module Memory Map .............................................................................................
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Tables Table Number 16-44 16-45 16-46 16-47 16-48 16-49 16-50 16-51 16-52 16-53 16-54 16-55 16-56 16-57 16-58 16-59 16-60 16-61 16-62 16-63 16-64 16-65 16-66 16-67 16-68 16-69 16-70 16-71 16-72 16-73 16-74 16-75 16-76 16-77 16-78 16-79 16-80 16-81 16-82 16-83 16-84 Title Page Number MIIMCFG Field Descriptions............................................................................................. 16-70 MIIMCOM Descriptions...............................................................................
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Tables Table Number 16-85 16-86 16-87 16-88 16-89 16-90 16-91 16-92 16-93 16-94 16-95 16-96 16-97 16-98 16-99 16-100 16-101 16-102 16-103 16-104 16-105 16-106 16-107 16-108 16-109 16-110 16-111 16-112 16-113 16-114 16-115 16-116 16-117 16-118 16-119 16-120 16-121 16-122 16-123 16-124 16-125 Title Page Number TEDF Field Descriptions .................................................................................................... 16-92 TSCL Field Descriptions ............................................
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Tables Table Number 16-126 16-127 16-128 16-129 16-130 16-131 16-132 16-133 16-134 16-135 16-136 16-137 16-138 16-139 16-140 16-141 16-142 16-143 16-144 16-145 16-146 16-147 16-148 16-149 16-150 16-151 16-152 16-153 16-154 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 18-1 18-2 18-3 Title Page Number Shared Signals................................................................................................................... 16-123 Steps for Minimum Register Initialization..............................
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Tables Table Number 18-4 18-5 18-6 18-7 18-8 18-9 18-10 18-11 18-12 18-13 18-14 18-15 18-16 18-17 18-18 18-19 18-20 18-21 18-22 18-23 19-1 19-2 19-3 19-4 19-5 19-6 19-7 19-8 19-9 20-1 20-2 21-1 21-2 21-3 21-4 21-5 21-6 21-7 21-8 A-1 A-2 Title Page Number URBR Field Descriptions ..................................................................................................... 18-5 UTHR Field Descriptions ...................................................................................................
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Tables Table Number A-3 A-4 A-5 A-6 A-7 A-8 A-9 A-10 A-11 A-12 A-13 A-14 A-15 A-16 A-17 A-18 A-19 A-20 A-21 A-22 A-23 A-24 B-1 Title Page Number Watchdog Timer (WDT) Registers ........................................................................................ A-3 Real Time Clock (RTC) Registers ......................................................................................... A-3 Periodic Interval Timer (PIT) Registers...........................................................................
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About This Book This reference manual defines the functionality of the MPC8308. The device is a cost-effective, low-power, highly integrated host processor that addresses the requirements of networking applications such as low-end printing, smart grid, home energy gateways, data concentrators, wireless LAN access points, femto base stations, and industrial applications, such as industrial control and factory automation.
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• • • • • • • • • their functions. In addition, the interrupt configuration, control, and status registers are described in this chapter. Chapter 9, “DDR Memory Controller,” describes the DDR2 memory controller of the device. This fully programmable controller supports most DDR memories available today, including both buffered and unbuffered devices. Dynamic power management and auto-precharge modes simplify memory system design.
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• • • • • • Chapter 18, “DUART,” describes the (dual) universal asynchronous receiver/transmitters (UARTs) which feature a PC16552D-compatible programming model. These independent UARTs are provided specifically to support system debugging. Chapter 19, “Serial Peripheral Interface,” describes the MPC8308 serial peripheral interface (SPI) that allows the exchange of data between the MPC8308 and MPC83xx family of devices.
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regarding bus timing, signal behavior, and AC, DC, and thermal characteristics, as well as other design considerations. For more information on other device documentation, refer to http://www.freescale.com. Conventions This document uses the following notational conventions: cleared/set When a bit takes the value zero, it is said to be cleared; when it takes a value of one, it is said to be set.
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Signal Conventions OVERBAR lowercase_italics lowercase_plaintext An overbar indicates that a signal is active-low. Lowercase italics is used to indicate internal signals. Lowercase plain text is used to indicate signals that are used for configuration. Acronyms and Abbreviations Table 1 contains acronyms and abbreviations used in this document. Table 1.
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Table 1.
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Table 1.
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MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev.
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Chapter 1 Overview This document provides an overview of the MPC8308 PowerQUICC II Pro processor features, including a block diagram showing the major functional components. MPC8308 is a cost-effective, low-power, highly integrated host processor. The device extends the PowerQUICC family, adding higher CPU performance, additional functionality, and faster interfaces while addressing the requirements related to time-to-market, price, power consumption, and package size. 1.
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Overview • • — Enhanced version of the MPC603e core — High-performance, superscalar processor core with a four-stage pipeline and low interrupt latency times — Floating-point, dual integer units, load/store, system register, and branch processing units — 16-Kbyte instruction cache and 16-Kbyte data cache with lockable capabilities — Capable of completing two MACs every three cycles — Dynamic power management — Enhanced hardware program debug features — Software-compatible with Freescale processor familie
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Overview • • – Per-packet configurable acceleration – Recognition of VLAN, stacked (queue in queue) VLAN, 802.2, PPPoE session, MPLS stacks, and ESP/AH IP-security headers – Transmission from up to eight physical queues – Reception to up to eight physical queues — Full- and half-duplex Ethernet support (1000 Mbps supports only full-duplex): – IEEE Std. 802.
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Overview — — — — — • • • 128-byte maximum payload size Virtual channel 0 only Traffic class 0–7 Full 64-bit decode with 32-bit wide windows Four outbound translation address windows – Support for mapping 32-bit internal local memory space to an external 32- or 64-bit address space and translating that address within the PCI Express space — Four inbound translation address windows corresponding to defined PCI Express BARs – The first BAR is 32-bits can be programmed to use on-chip register access – The
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Overview • — Master or slave I2C mode support — On-chip digital filtering rejects spikes on the bus General purpose DMA engine — Support for the DMA engine with the following features: – Four DMA channels – All data movement via dual-address transfers: read from source, write to destination – Transfer control descriptor (TCD) organized to support two-deep, nested transfer operations – Channel activation using one of two methods (for both the methods, one activation per execution of the minor loop is requi
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Overview • • — Supports block sizes of 1 ~ 4096 bytes — Supports the write protection switch for write operations — Supports synchronous abort — Supports pause during the data transfer at block gap — Supports SDIO read wait and suspend resume operations — Supports Auto CMD12 for multi-block transfer — Host can initiate non-data transfer command while data transfer is in progress — Allows cards to interrupt the host in 1 and 4-bit SDIO modes — Embodies a fully configurable 128  32-bit FIFO for read/write
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Overview 1.2 MPC8308 Architecture Overview The following sections describe the major functional units of this device. 1.2.1 e300 Core The device contains the e300c3 processor core, which is an enhanced version of the MPC603e core (used in previous generations of PowerQUICC II processors). Enhancements include integrated parity checking, dual integer units, and other performance-enhancing features. The e300 core is upward software-compatible with existing MPC603e core-based products.
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Overview interrupt routines or other important (time-sensitive) instruction sequences into the instruction cache. It allows data to be locked into the data cache, which may be important to code that must have deterministic execution. The e300 core has high-performance 64-bit data bus and 32-bit address bus interfaces to the rest of the device. The e300 core supports single-beat and burst data transfers for memory accesses and memory-mapped I/O operations.
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Overview Figure 1-2 provides a block diagram of the e300 core that shows how the execution units (IU1, IU2, FPU, BPU, LSU, and SRU) operate independently and in parallel. Note that this is a conceptual diagram that does not attempt to show how these features are physically implemented on the chip.
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Overview 1.2.2 DDR2 Memory Controller This fully programmable DDR2 SDRAM controller supports most JEDEC standard 8 or 16 DDR2 memories available today, including buffered and unbuffered DIMMs. However, mixing non registered and registered DIMMs in the same system is not supported.
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Overview To provide for quality of service, transmission from up to eight queues is supported with priority-based queue selection. Arbitration is a modified weighted round-robin queue selection with fair bandwidth allocation. On receive, packets may be distributed to any of the 64 virtual receive queues overlaid onto the 8 physical receive queues. A table-oriented queue filing strategy is provided based on 16 header fields or flags. Frame rejection is supported for filtering applications.
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Overview The host and device functions are both configured to support the following four types of USB transfers: • Bulk • Control • Interrupt • Isochronous CSB TX Buffer RX Buffer ULPI Dual-Role Module (DR) Figure 1-3. USB Controllers Port Configuration 1.2.6.1 • • • • • • • 1.2.7 USB Dual-Role Controller Designed to comply with Universal Serial Bus Revision 2.
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Overview such, it supports a minimal glue logic interface to SRAM, EPROM, NOR Flash EPROM, NAND Flash EPROM, Flash EPROM, burstable RAM, and other peripherals. The eLBC also includes a number of data checking and protection features such as data parity generation and checking, write protection, and a bus monitor to ensure that each bus cycle is terminated within a user-specified period. The eLBC provides two Write Enable signals to allow single-byte write access to external 16-bit eLBC slave devices.
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Overview • • 1.2.
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Overview 1.2.9 I2C Interface The inter-IC (IIC or I2C) bus is a two-wire—serial data (SDA) and serial clock (SCL)— bidirectional serial bus that provides a simple, efficient method of data exchange between the system and other devices, such as microcontrollers, EEPROMs, real-time clock devices, A/D converters, and LCDs. The two-wire bus minimizes the interconnections between devices.
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Overview 1.2.11 Dual Universal Asynchronous Receiver/Transmitter (DUART) The device includes a Dual universal Asynchronous Reciever/Transmitter (DUART) intended for use in maintenance, bring up, and debug systems. The device provides a standard two-wire data (TXD and RXD) for each port. The DUART is a slave interface. An interrupt is provided to the interrupt controller. Interrupts are generated for transmit, receive, and line status. The DUART supports full-duplex operation.
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Overview • audio and video consumer electronic devices. The physical form factor, pin assignments, and data transfer protocol are forward-compatible with the old MMC. SDIO Under the SD protocol, the SD cards can be categorized as a memory card, I/O card, or combo card. The memory card invokes a copyright protection mechanism that complies with the security of the SDMI standard. The I/O card provides high-speed data I/O with low power consumption for mobile electronic devices.
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Overview MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev.
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Chapter 2 Signal Descriptions This chapter describes the external signals of the device. It is organized into the following sections: • Overview of signals and cross references for signals that serve multiple functions, including a list ordered by functional block. • List of output signal states at reset NOTE A bar over a signal name indicates that the signal is active low, such as MWE. Active-low signals are referred to as asserted (active) when they are low and negated when they are high.
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Signal Descriptions MDQ[0:31] DDR2 Memory Interface 82 Signals MECC[0:7] MDM[0:3] MDM[8] MDQS[0:3] MDQS[8] MBA[2:0] MA[13:0] MWE MRAS MCAS MCS[0:1] MCKE MCK[0:2] MCK[0:2] MODT[0:1] MVREF GPIO/ eTSEC2 24 Signals GPIO[0]/TSEC2_COL GPIO[0]/TSEC2_CRS GPIO[1]/TSEC2_TX_ER GPIO[2]/TSEC2_GTX_CLK GPIO[3]/TSEC2_RX_CLK GPIO[4]/TSEC2_RX_DV GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5:7] GPIO[5:7]/TSEC2_RXD[3:1] GPIO[8]/TSEC2_RXD[0] GPIO[9]/TSEC2_RX_ER GPIO[10]/TSEC2_TX_CLK/TSEC2_GTX_CLK125 GPIO[11]/TSEC2_TXD[3] GPIO[12]
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Signal Descriptions USBDR_PWR_FAULT USBDR_CLK USBDR_DIR USBDR_NXT USBDR_TXDRXD[0:7] USB Interface 15 Signals USBDR_PCTL[0:1] USBDR_STP IIC_SDA1 IIC_SCL1 I2C Interface 4 Signals IIC_SDA2/CKSTOP_OUT IIC_SCL2/CKSTOP_IN TSEC_TMR_GCLK TSEC_TMR_CLK/GPIO[8] TSEC_TMR_PP[1:2] TSEC_TMR_PP[3]/GPIO[13] IEEE 1588 Interface 9 Signals TSEC_TMR_ALARM[1] TSEC_TMR_ALARM[2]/GPIO[14] TSEC_TMR_TRIG[1]/GPIO[11] TSEC_TMR_TRIG[2]/GPIO[12] TXA, TXA RXA, RXA SD_IMP_CAL_RX PCIExpress PHY 10 Signals SD_REF_CLK, SD_REF_CLK
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Signal Descriptions Table 2-1. MPC8308 Signal Reference by Functional Block (continued) Name Description Functional Block No.
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Signal Descriptions Table 2-1. MPC8308 Signal Reference by Functional Block (continued) Name Description Functional Block No.
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Signal Descriptions Table 2-1. MPC8308 Signal Reference by Functional Block (continued) Name Description Functional Block No.
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Signal Descriptions Table 2-1. MPC8308 Signal Reference by Functional Block (continued) Name Description Functional Block No.
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Signal Descriptions Table 2-1. MPC8308 Signal Reference by Functional Block (continued) Name Description Functional Block No.
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Signal Descriptions Table 2-1. MPC8308 Signal Reference by Functional Block (continued) Name Description Functional Block No.
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Signal Descriptions Table 2-1. MPC8308 Signal Reference by Functional Block (continued) Name Description Functional Block No.
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Signal Descriptions Table 2-1. MPC8308 Signal Reference by Functional Block (continued) Name Description Functional Block No.
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Signal Descriptions Table 2-1. MPC8308 Signal Reference by Functional Block (continued) Name Description Functional Block No.
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Signal Descriptions Table 2-1. MPC8308 Signal Reference by Functional Block (continued) Name Description Functional Block No.
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Signal Descriptions Table 2-2.
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Signal Descriptions Table 2-2. Output Signal States During System Reset (continued) Interface Signal USBDR_PCTL[0:1] USBDR_STP State During Reset Port control 0–1 Low End of a transfer on the bus High MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev.
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Signal Descriptions MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev.
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Chapter 3 Memory Map This chapter describes the MPC8308 memory map. The internal memory-mapped registers are described, including a complete listing of all memory-mapped registers with cross references to the sections detailing descriptions of each. 3.1 Internal Memory-Mapped Registers All of the memory-mapped registers in the device are contained within a 1-Mbyte address region. To allow for flexibility, the base address of the memory-mapped registers is re-locatable in the local address space.
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Memory Map In certain specific cases, reserved bits should not be cleared but should keep their reset value. Thus, the software should perform a ‘read-modify-write’ and make sure that it does not change the reset value of those bits. The description of the specific bits indicate when this is needed. Cross-references are provided to the IMMRBAR maps for each individual block. A complete listing of all registers is provided in Appendix A, “Complete List of Configuration, Control, and Status Registers.
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Memory Map Table 3-1. IMMR Memory Map (continued) Block Base Address Block Actual Size Window Section/ Page 16.5/16-9 0x2_4000–0x2_4FFF eTSEC1 4 Kbytes 4 Kbytes 0x2_5000–0x2_5FFF eTSEC2 4 Kbytes 4 Kbytes 0x2_6000–0x2_BFFF Reserved — 28.6 Kbytes — 0x2_C000–0x2_DFFF DMAC 8 Kbytes 8 Kbytes 12.2/12-2 0x2_E000–0x2_FFFF eSDHC 8 Kbytes 8 Kbytes 11.4/11-5 0x2_F000–0xE_2FFF Reserved — 737.2 Kbytes — 0xE_3000–0xE_30FF SerDes — 256 bytes 15.
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Memory Map MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev.
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Chapter 4 Reset, Clocking, and Initialization The reset, clocking, and control signals offer many options for operating the device. Various modes and features can be configured during hard reset or power-on reset. Most configurable features are loaded to the device through a reset configuration word, and a few device signals are used as reset configuration inputs during the reset sequence. 4.1 External Signals The following sections describe the reset and clock signals in detail. 4.1.
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Reset, Clocking, and Initialization Table 4-1. System Control Signals (continued) Signal I/O Description CFG_RESET_ SOURCE[0:3] I Reset configuration word source selection. These signals are on device pins that have other functions when the device is not in reset. They are sampled during the assertion of PORESET to determine the interface from which the device loads the reset configuration words. State Meaning See Section 4.3.1.1, “Reset Configuration Word Source.
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Reset, Clocking, and Initialization Table 4-2. External Clock Signals (continued) Signal I/O Description TSECn_TX_CLK/ TSECn_GTX_CLK125 I Ethernet Transmit Clock. TSECn_TX_CLK is used in the MII mode. TSECn_GTX_CLK125 is the 125-MHz clock used in the RGMII mode. Timing Assertion/Negation—For timing information, see MPC8308 PowerQUICC II Pro Processor Hardware Specification. Reset State Always input. 4.
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Reset, Clocking, and Initialization Table 4-3. Reset Causes (continued) Name Description Checkstop reset If the core enters checkstop state and the checkstop reset is enabled (RMR[CSRE] = 1), the checkstop reset is asserted. The enabled checkstop event then generates an internal hard reset sequence. Software hard reset A hard reset sequence can be initialized by writing to a memory-mapped register (RCR). 4.2.1.
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Reset, Clocking, and Initialization 4.2.2 Power-On Reset Flow Assertion of the PORESET external signal initiates the power-on reset flow. PORESET should be asserted externally for at least 32 input clock cycles after stable external power to the device is applied. Directly after the negation of PORESET, the device starts the configuration process. The device asserts HRESET throughout the power-on reset process, including configuration.
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Reset, Clocking, and Initialization Figure 4-1 shows a timing diagram of the power-on reset flow. SYS_CLK_IN Stable clock PORESET (Input) Min. 32 SYS_CLK_IN cycles PLLs are locked (no external indication) HRESET (Output) TRST (Input) Reset Configuration Input Signals Reset Configuration Words Loading Start loading reset configuration words End loading reset configuration words. Duration depends on source Figure 4-1.
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Reset, Clocking, and Initialization Figure 4-2 shows a timing diagram of the hard reset flow. SYS_CLK_IN Stable clock PORESET (Input) HRESET (Input or Output) TRST (Input) Reset Configuration Input Signals Reset Configuration Words Loading Start loading reset configuration words End loading reset configuration words. Duration depends on source Figure 4-2. Hard Reset Flow 4.
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Reset, Clocking, and Initialization described in Section 4.5.1.3, “Reset Status Register (RSR),” and Section 4.5.2.1, “System PLL Mode Register (SPMR).” NOTE Implement one of the following methods to control the selection between the reset and non-reset function of these pins. • • 4.3.1.1 Resistors. Use pull-up or pull-down resistors to set the desired value on the reset configuration input signals. During the power-on and hard reset sequences, these signals are inputs to the device.
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Reset, Clocking, and Initialization 4.3.1.2 Selecting Reset Configuration Input Signals The example described in Table 4-6 shows how the user should pull down or pull up the reset configuration input signal (CFG_RESET_SOURCE). The reset sequence duration is measured from the negation of PORESET to the negation of HRESET. Note that the duration mentioned in Table 4-6 is typical, and does not represent cases in which the process of loading the reset configuration word had to be retried due to errors.
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Reset, Clocking, and Initialization 4.3.2.1 Reset Configuration Word Low Register (RCWLR) RCWLR is shown in Figure 4-3. This read-only register obtains its values according to the reset configuration word low loaded during the reset flow. Field 0 1 2 LBCM DDRCM 3 4 SVCOD 7 8 SPMF 9 — 15 COREPLL 16 31 Field — Figure 4-3. Reset Configuration Word Low Register (RCWLR) Table 4-7 defines the RCWLR bit fields. Table 4-7.
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Reset, Clocking, and Initialization Table 4-8 describes the setting of SVCOD bits. Table 4-8. System PLL VCO Division Reset Configuration Word Low Register (RCWLR) Bits Field Name Value (Binary) VCO Division Factor 2–3 SVCOD 00 2 01 4 10 8 11 Reserved NOTE For the frequency of operation for MPC8308, 00 is the only applicable value of SVCOD. 4.3.2.1.
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Reset, Clocking, and Initialization 4.3.2.2 Reset Configuration Word High Register (RCWHR) RCWHR is shown in Figure 4-4. This read-only register gets its values according to the reset configuration word high loaded during the reset flow. Offset 0x0_0904 Access: Read/Write 0 3 Field Field CORE DIS — 16 18 TSEC1M 4 19 5 6 7 8 9 BMS BOOTSEQ SWEN 21 22 11 ROMLOC 27 TSEC2M — 12 13 14 RLEXT 28 TLE 29 15 — 30 31 — Figure 4-4.
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Reset, Clocking, and Initialization Table 4-10. Reset Configuration Word High Bit Settings (continued) Bits Name Description 12–13 RLEXT Boot ROM location extension. This bit combined with bit ROMLOC determines where the device boots from. See Section 4.3.2.2.3, “Boot ROM Location,” for more information. 00 Legacy mode—allows for booting from on-chip peripherals. For more information, see Table 4-13. 01 NAND Flash mode—allows for booting from NAND flash devices. For more information, see Table 4-13.
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Reset, Clocking, and Initialization 4.3.2.2.2 Boot Sequencer Configuration The boot sequencer configuration options, shown in Table 4-12, allow the boot sequencer to load configuration data from the serial ROM located on the I2C port before the host tries to configure the device. These options also specify normal or extended I2C addressing modes. See Section 17.4.5, “Boot Sequencer Mode.” Table 4-12.
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Reset, Clocking, and Initialization bits, as shown in Table 4-10. Accesses to the boot vector and the default boot ROM region of the local address map are directed to the interface specified by this field. Table 4-13.
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Reset, Clocking, and Initialization 4.3.2.2.5 eTSEC2 Mode The eTSEC2 mode reset configuration word field, shown in Table 4-15, selects the protocol used by the eTSEC2 controller. Table 4-15. eTSEC2 Mode Configuration Reset Configuration Word High Register (RCWHR) Bits Field Name Value (Binary) 19–21 TSEC2M 000 The eTSEC2 controller operates in the MII protocol, using only four transmit data signals and four receive data signals.
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Reset, Clocking, and Initialization Table 4-17 shows addresses that should be used to contain the reset configuration words. Byte addresses that do not appear in this table have no effect on the configuration of the device. The values of the bytes in Table 4-17 are always read on byte lane LD[0:7] regardless of the port size. . Table 4-17.
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Reset, Clocking, and Initialization The device uses FCM to load the reset configuration from NAND Flash. The device reads 512 bytes if small-page size NAND Flash is used or 2048 bytes if large-page NAND Flash is used. The local bus controller’s registers setting are set according to Table 4-19. Table 4-19. Local Bus Controller Setting When Loading RCW CFG_RESET_SOURCE[0:3] 4.3.3.
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Reset, Clocking, and Initialization 4.3.3.2.3 EEPROM Data Format in Reset Configuration Mode The I2C module expects that a particular data format be used for data in the EEPROM. A preamble should be the first 3 bytes programmed into the EEPROM. It should have a value of 0xAA_55AA. The I2C module checks to ensure that this preamble is correctly detected before proceeding further.
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Reset, Clocking, and Initialization contains information additional to the reset configuration words, which should be loaded in the functional state after the device completes its reset flow.
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Reset, Clocking, and Initialization 4.3.3.2.4 Reset Configuration Load Fail Failure of reset configuration load by the I2C boot sequencer can be caused by an incorrect EEPROM data structure or I2C bus problem. If a reset configuration load failure occurs, due to preamble fail or any other I2C bus error detection, the device continuously attempts to reload the hard reset configuration words from the I2C bus.
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Reset, Clocking, and Initialization Table 4-22 defines the hard-coded reset configuration word high fields values. These values select hard-coded reset configuration words options, as described in Section 4.3.1.1, “Reset Configuration Word Source.” Table 4-22. Hard-Coded Reset Configuration Word High Field Values Bits Name Field Values when CFG_RESET_SOURCE[0–3] = 1000–1100 1000 1001 1010 1011 Meaning 1100 0–3 Reserved 4 COREDIS 5 BMS 1 Boot memory space is 0xFF80_0000– 0xFFFF_FFFF.
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Reset, Clocking, and Initialization Figure 4-7 shows the internal distribution of clocks within the device.
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Reset, Clocking, and Initialization The csb_clk frequency is derived as follows: csb_clk = [SYS_CLK_IN] × SPMF The csb_clk serves as the clock input to the e300 core. A second PLL inside the core multiplies up the csb_clk frequency to create the internal clock for the core (core_clk). The system and core PLL multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL), which is loaded at power-on reset or by one of the hard-coded reset options. See Section 4.
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Reset, Clocking, and Initialization 4.4.3 Ethernet Clocking When running in RGMII mode, the reference clocks are TSECn_GTX_CLK125 and TSECn_RX_CLK input on the eTSEC1 and eTSEC2 interface. This can either be a 2.5- or 3.3-V signal. When running in the MII mode, the reference clocks are TSECn_TX_CLK and TSECn_RX_CLK input on the eTSEC1 and eTSEC2 interface. This can be either a 2.5- or 3.3-V signal. For more information, see Chapter 16, “Enhanced Three-Speed Ethernet Controllers.” 4.
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Reset, Clocking, and Initialization 4.5.1.3 Reset Status Register (RSR) RSR, shown in Figure 4-8, captures various reset events in the device. The RSR accumulates reset events. For example, because software watchdog expiration results in a hard reset, SWRS and HRS are all set after a software watchdog reset. This register returns to its reset value only when power-on reset occurs.
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Reset, Clocking, and Initialization Table 4-25. Reset Status Register Field Descriptions (continued) Bits Name Description 29 BMRS Bus monitor reset status. When a bus monitor expire event (which causes a reset) is detected, BMRS is set and remains set until the software clears it. BMRS can be cleared by writing a 1 to it (writing zero has no effect). 0 No bus monitor reset event. 1 Bus monitor reset event. 30 — 31 HRS 4.5.1.4 Reserved Hard reset status.
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Reset, Clocking, and Initialization 4.5.1.5 Reset Protection Register (RPR) RPR, shown in Figure 4-10, prevents unintended software reset requests caused by writes to the reset control register (RCR). To disable a write to the reset control register (RCR), the user should write a 1 to RCER[CRE]. Address 0x0_0918 Access: User read/write 0 15 R RCPW W Reset All zeros 16 31 R RCPW W Reset All zeros Figure 4-10. Reset Protection Register (RPR) Table 4-27 defines the bit fields of RPR.
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Reset, Clocking, and Initialization Table 4-28 defines the bit fields of RCR. Table 4-28. RCR Bit Settings Bits Name 0–29 — 30 Description Reserved, should be cleared. SWHR Software hard reset. Setting this bit causes the device to begin a hard reset flow. This bit returns to its reset state during the reset sequence, so reading it always returns all zeros. 31 — 4.5.1.7 Reserved.
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Reset, Clocking, and Initialization Table 4-30. Clock Configuration Registers Memory Map (continued) Address Register 0x0_0A08 System clock control register (SCCR) 0x0_0A0C– 0x0_0AFC Reserved, should be cleared 4.5.2.1 Access Reset Section/Page R/W 0x5550_0010 4.5.2.3/4-32 — — — System PLL Mode Register (SPMR) SPMR is shown in Figure 4-13. It obtains its values according to the reset configuration input signal and the reset configuration word low loaded during the reset flow.
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Reset, Clocking, and Initialization 4.5.2.2 Output Clock Control Register (OCCR) The OCCR shown in Figure 4-14, controls the device output clocks. It is possible to control some output clock modes by writing to this memory-mapped register as described below. Address 0x0_0A04 Access: Read/Write 0 15 R — W Reset All zeros 16 R W Reset 17 18 19 23 MCK1O MCK2O MCK0O E, E, E, MCK_ MCK_B MCK_B B0OE 1OE 2OE 1 1 1 — 0 0 0 24 25 31 LCLK0E 0 0 1 — 0 0 0 0 0 0 0 Figure 4-14.
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Reset, Clocking, and Initialization 4.5.2.3 System Clock Control Register (SCCR) The system clock control register (SCCR), shown in Figure 4-15, controls device units that have a configurable clock ratio. NOTE The SCCR is not meant for dynamic On/Off of the clock to the module. This can be only disabled once after reset. To use the module again, a power-on reset cycle has to take place.
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Reset, Clocking, and Initialization Table 4-33. SCCR Bit Descriptions (continued) Bits Name 10–11 PCIEXPCM 12–25 — 26–27 DMACCM 28–31 — Description PCIEXP1 clock mode. Define the clock mode for the PCI Express 1 controller. 00 PCIEXP1 clock is disabled. 01 PCIEXP1 clock is enabled. Reserved DMACCM 00 DMAC core clock is disabled. 01 DMAC core clock/csb_clk ratio is 1:1. 10 DMAC core clock/csb_clk ratio is 1:2. 11 DMAC core clock/csb_clk ratio is 1:3.
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Reset, Clocking, and Initialization MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev.
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Chapter 5 System Configuration This chapter describes several functions that control the local access windows, system configuration, protection, and general utilities. These functions are discussed in the following sections: • Section 5.1, “Local Memory Map Overview and Example” • Section 5.2, “System Configuration” • Section 5.3, “Software Watchdog Timer (WDT)” • Section 5.4, “Real Time Clock (RTC) Module” • Section 5.5, “Periodic Interval Timer (PIT)” • Section 5.
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System Configuration Figure 5-1 shows an example memory map. 0 Example Local Memory Map DDR2 SDRAM Memory 0x8000_0000 Local Bus SRAM 0xA000_0000 I/O Configuration Registers Local Bus Flash 0xFFFF_FFFF IMMR Boot ROM Figure 5-1. Local Memory Map Example Table 5-2 shows an example of local access window settings. Table 5-2.
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System Configuration 5.1.1 Address Translation and Mapping In addition to any address translation performed by the e300 core MMU, three distinct types of translation and mapping operations are performed on transactions at the integrated device level.
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System Configuration 0xFF40_0000, and this base address value can be modified by writing to this register. For more information, see Section 5.1.4.1, “Internal Memory Map Registers Base Address Register (IMMRBAR).” NOTE Although it is legal to use the 3-Mbyte space consecutive to the 1 Mbyte of the IMMR (for example, if IMMRBAR is 0xFF40_0000, the 3-Mbyte address space consecutive to it is 0xFF50_0000–0xFF7F_FFFF), it is not recommended.
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System Configuration Table 5-4. Local Access Register Memory Map (continued) Local Access—Block Base Address 0x0_0000 Local Memory Offset (Hex) Register Access Reset Section/Page 0x0_0030 eLBC local access window 2 base address register (LBLAWBAR2) R/W 0x0000_0000 5.1.4.3/5-7 0x0_0034 eLBC local access window 2 attribute register (LBLAWAR2) R/W 0x0000_0000 5.1.4.4/5-8 0x0_0038 eLBC local access window 3 base address register (LBLAWBAR3) R/W 0x0000_0000 5.1.4.
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System Configuration memory map register is 0xFF40_0000. Because IMMRBAR is at offset 0x0 from the beginning of the local access registers, the IMMRBAR always points to itself. 5.1.4.1.1 Updating IMMRBAR Updates to IMMRBAR that relocate the entire 1-Mbyte region of the internal memory block require special treatment. The effect of the update must be guaranteed to be visible by the mapping logic before an access to the new location is seen.
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System Configuration 5.1.4.2 Alternate Configuration Base Address Register (ALTCBAR) The alternate configuration base address register (ALTCBAR) is used to define the base address for an alternate 1-Mbyte region of configuration space to be used by the boot sequencer. By loading the proper boot sequencer command in the serial ROM, the base address in the ALTCBAR can be combined with the 20 bits of address offset supplied from the serial ROM to generate a 32-bit address.
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System Configuration Table 5-7 defines the bit fields of LBLAWBAR0–LBLAWBAR3. ‘ Table 5-7. LBLAWBAR0–LBLAWBAR3 Bit Settings Bits Name 0–19 Description BASE_ADDR Identifies the 20 most-significant address bits of the base of local access window n. The specified base address should be aligned to the window size, as defined by LBLAWARn[SIZE]. 20–31 — 5.1.4.3.1 Reserved. Write has no effect, read returns 0.
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System Configuration Table 5-9. LBLAWAR0–LBLAWAR3 Bit Settings (continued) 1–25 — 26–31 SIZE 5.1.4.4.1 Reserved. Write has no effect, read returns 0. Identifies the size of the window from the starting address. Window size is 2(SIZE+1) bytes. 000000–001010 Reserved. Window is undefined. 001011 4 Kbytes 001100 8 Kbytes 001101 16 Kbytes . . . . . . . 2(SIZE+1) bytes 011110 2 Gbytes 011111–111111 Reserved. Window is undefined.
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System Configuration Table 5-11 defines the bit fields of PCIEXP1LAWBAR. ‘ Table 5-11. PCIEXP1LAWBAR Bit Settings Bits Name 0–19 Description BASE_ADDR Identifies the 20 most-significant address bits of the base of local access window. The specified base address should be aligned to the window size, as defined by PCIEXP1LAWAR[SIZE]. 20–31 — 5.1.4.6 Reserved. Write has no effect, read returns 0.
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System Configuration 5.1.4.7 DDR Local Access Window n Base Address Registers (DDRLAWBAR0–DDRLAWBAR1) The DDR local access window n base address registers (DDRLAWBAR0–DDRLAWBAR1) are shown in Figure 5-8. Offset 0xA0 0xA8 Access: Read/Write 0 19 20 R BASE_ADDR W — All zeros1 Reset 1 31 The reset value of DDRLAWBAR0[BASE_ADDR] depends on the reset configuration word high values. See Section 5.1.4.7.1, “DDRLAWBAR0[BASE_ADDR] Reset Value,” for a detailed description Figure 5-8.
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System Configuration 5.1.4.8 DDR Local Access Window n Attributes Registers (DDRLAWAR0–DDRLAWAR1) The DDR local access window n attributes registers (DDRLAWAR0–DDRLAWAR1) are shown in Figure 5-9. Offset 0xA4 0xAC 0 R W Access: Read/Write 1 EN 25 26 — 31 SIZE All zeros1,2 Reset 1 The reset value of DDRLAWAR0[EN] depends on the reset configuration word high values. See Section 5.1.4.8.1, “DDRLAWAR0[EN] and DDRLAWAR0[SIZE] Reset Value,” for a detailed description.
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System Configuration Table 5-16 defines the reset value DDRLAWAR0[EN] and DDRLAWAR0[SIZE]. ‘ Table 5-16. DDRLAWAR0[EN] Reset Value RCWHR[ROMLOC] RLEXT1 DDRLAWAR0[EN] Reset Value 000 00 1 e300 core boot performed from a DDR SDRAM device. DDR 8-Mbyte (2(22+1)) local access window is enabled. 000 01 0 e300 core boot not performed from a DDR SDRAM device Else – 0 e300 core boot not performed from a DDR SDRAM device. 1 Description For more information, see Section 4.3.2.
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System Configuration The PCI Express interface has outbound address translation units that map the local address into an external address space. These other mapping functions are configured by programming the configuration, control, and status registers of the individual interfaces. Note that there is no need to have a one-to-one correspondence between local access windows and chip select regions or outbound windows.
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System Configuration 5.1.11 Accessing Internal Memory from External Masters In addition to being accessible by the e300 processor, the IMMR memory window is accessible from external interfaces. This allows external masters on the I/O ports to configure the device. External masters do not need to know the location of the IMMR memory in the local address map.
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System Configuration 5.2.2 System Configuration Registers This section discusses the system configuration registers. 5.2.2.1 System General Purpose Register Low (SGPRL) The system general purpose register low (SGPRL), shown in Figure 5-10, can be used by software for any purpose. The values set in this register have no effect on the internal hardware. Offset 0x00100 Access: Read/Write 0 31 R GP W Reset All zeros Figure 5-10.
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System Configuration 5.2.2.3 System Part and Revision ID Register (SPRIDR) The SPRIDR, shown in Figure 5-12, provides information about the device and revision numbers. Offset 0x00108 Access: Read only 0 23 24 31 R PARTID REVID W Reset See Table 5-22 and Table 5-23 for reset values of this register. Figure 5-12. System Part and Revision ID Register (SPRIDR) Table 5-21 defines the bit fields of SPRIDR. Table 5-21. SPRIDR Bit Settings Bits Name Description 0–23 PARTID Part identification.
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System Configuration whenever an internal unit requests mastership of the coherent system bus (CSB). The SPCR also includes some other control functions. Offset 0x00110 0 R Access: Read/Write 1 — W 2 3 7 EN_SEONAK_ FIX Reset W 9 OPT TBEN 10 11 COREPR 12 15 — All zeros 16 R 8 17 — 18 19 TSECDP 20 21 22 23 24 TSECBDP TSECEP Reset 31 — All zeros Figure 5-13. System Priority Configuration Register (SPCR) Table 5-24 defines the bit fields of SPCR. ‘ Table 5-24.
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System Configuration Table 5-24. SPCR Bit Settings (continued) Bits Name Description 20–21 TSECBDP eTSEC buffer descriptor priority. Selects the CSB request priority driven by eTSEC1 and eTSEC2 when they require to transfer a buffer descriptor (BD) on this bus. The level of priority can be chosen from four possible levels. 00 Level 0 (lowest priority) 01 Level 1 10 Level 2 11 Level 3 (highest priority 22–23 TSECEP TSEC emergency priority.
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System Configuration Figure 5-14 shows SICRL. Offset 0x00114 Access: Read/Write 0 1 R 2 Reserved W Reset 4 SPI 0 0 0 0 8 9 10 11 12 R 5 0 0 0 7 IRQ_B 0 0 0 15 I2C2 — 6 UART 0 W Reset 3 — 0 0 0 0 16 0 23 R — W Reset 0 0 0 24 25 26 R 0 0 Reset 0 1 0 0 31 ETSEC1_A1 W 0 — 0 0 0 0 0 0 0 Bit #25 depends on the TSEC1M in the RCW. If it is set to RGMII, this bit is set to 1 on reset; for other values of TSEC1M, this is zero. Figure 5-14.
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System Configuration Table 5-25.
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System Configuration 5.2.2.6 System I/O Configuration Register High (SICRH) The system I/O configuration register high (SICRH), shown in Figure 5-15, controls the multiplexing of the rest of the device I/O pins. Each bit or set of bits in this register selects which function is used by a certain group of the device pins.
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System Configuration Table 5-26.
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System Configuration Table 5-26.
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System Configuration Table 5-26. SICRH Bit Settings (continued) SICRH[Bits] Value 0b00 0b01 0b10 0b11 Reset Value Bits Group Pin Function 0 Pin Function 1 Pin Function 2 Pin Function 3 24–26 — Reserved — — — — 27 TMROBI 28–29 — — — 30 TSOBI1 31 TSOBI2 See Table 5-27 for description and reset value. Reserved — — See Table 5-27 for description and reset value. 1 When SICRH[eSDHC_A] = 0b01, SD_CLK and SD_CMD are in High-Z state.
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System Configuration 2 If RCWH[ETSEC2M] is RGMII, the reset value is 1; otherwise, it is 0. NOTE An empty column cannot be used for this register. A function should be selected so that the column is non-empty. 5.2.2.7 Selection of Pin Functions During Reset Few functions muxed with the I/Os are needed only during the period when the device is in reset state. Those functionality are selected by default during the reset phase.
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System Configuration DDRCDR is shown in Figure 5-16. Offset 0x00128 Access: Read/Write 0 R W Reset 1 2 5 — DSO_EN DSO_PZ 0 0 0 0 0 0 6 9 10 11 DSO_NZ 0 0 0 0 0 16 0 28 R — W Reset 13 0 0 0 0 0 0 0 0 14 DDR_TYPE ODT (Reserved to 0) — 0 12 15 — 0 0 0 29 30 31 MVREF_SEL M_odr 0 0 0 0 0 0 0 — 0 Figure 5-16. DDR Control Driver Register (DDRCDR) Table 5-28 shows the bit definition of the DDRCDR. Table 5-28.
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System Configuration Table 5-28. DDRCDR Field Descriptions (continued) Bits Name 30 M_odr 31 — 5.2.2.10 Description Disable memory transaction reordering 0 Memory transaction reordering enabled 1 Memory transaction reordering disabled Reserved DDR Debug Status Register (DDRDSR) Figure 5-17 contains the debug status bits from the DDR SDRAM controller.
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System Configuration Figure 5-18 shows the PECR bit settings. Offset 0x00140 0 R W Access: Read/Write 1 2 3 15 LINK_RST CBRST CSR_RST — Reset All zeros 16 R W 17 25 DEV_TYPE — Reset 26 27 PRI_DATA 28 29 PRI_DES 30 31 PRI_PIO All zeros Figure 5-18. PCI Express Controller Registers (PECR1) Table 5-30 describes the bits of the PECR register. Table 5-30. PECR Field Description Bits Name Description 0 LINK_RST Link soft reset (active low).
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System Configuration Table 5-30. PECR Field Description (continued) Bits Name Description 28–29 PRI_DES DMA descriptor priority. This field is used to present priority level for CSB arbitration for PCI Express controller’s DMA requests. Bits 28–29 are used when the request belongs to descriptor fetch or update. 00 Level 0 (lowest priority) 01 Level 1 10 Level 2 11 Level 3 (highest priority) 30–31 PRI_PIO PIO priority.
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System Configuration Table 5-31 describes the bits of the SDHCCR register. Table 5-31. SDHCCR Field Description Bits Name Description 0 RD_PREFETCH_VAL This determines the prefetch byte count to be used if RD_PREFETCH_DISABLE is not set. 0 32 byte prefetch 1 64 byte prefetch 1 RD_PREFETCH_DISABLE Read prefetch disable.
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System Configuration 5.2.2.13 RTC Control Registers (RTCCR) The RTC control register controls the reset for the RTC. Figure 5-20 shows the RTCCR bit settings. Offset 0x00148 Access: Read/Write 0 15 R — W Reset All zeros 16 30 R — W Reset 31 RESET_RTC All zeros Figure 5-20. RTC Control Register (RTCCR) Table 5-32 describes the bits of the RTCCR register. Table 5-32. RTCCR Field Description Bits Name 0–30 Reserved 31 RESET_RTC 5.
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System Configuration Figure 5-21 shows a high-level block diagram of the WDT. Software Watchdog Timer System clock Reset or mcp Register Interface Figure 5-21. Software Watchdog Timer High-Level Block Diagram The software watchdog timer is enabled after reset to cause a hardware reset if it times out. The user has the option of disabling the software watchdog if it is not needed. If used, the software watchdog timer requires a special service sequence to be executed periodically.
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System Configuration 5.3.4 WDT Memory Map/Register Definition The WDT programmable register map occupies 16 bytes of memory-mapped space. Reading undefined portions of the memory map returns all zeros, and writing has no effect. All WDT registers are 16- or 32-bits wide, located on 16-bit address boundaries, and should be accessed as 16- or 32-bit quantities. All addresses used in this chapter are offsets from the WDT base, as defined in Chapter 3, “Memory Map.” Table 5-33 shows the WDT memory map.
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System Configuration Table 5-34 defines the bit fields of SWCRR. Table 5-34. SWCRR Bit Settings Bits Name Description 0–15 SWTC Software watchdog time count The SWTC field contains the modulus that is reloaded into the watchdog counter by a service sequence. When a new value is loaded into SWCRR[SWTC], the software watchdog timer is not updated until the servicing sequence is written to the SWSRR. If SWCRR[SWEN] is loaded with 0, the modulus counter does not count.
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System Configuration Table 5-35 defines the bit fields of SWCNR. Table 5-35. SWCNR Bit Settings Bits Name 0–15 — 16–31 Description Write reserved, read = 0 SWCN Software watchdog count field. The read-only SWCNR[SWCN] field reflects the current value in the watchdog counter. Writing to the SWCNR register has no effect, and write cycles are terminated normally. Reset initializes the SWCNR[SWCN] field to 0xFFFF.
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System Configuration 5.3.5 Functional Description This section provides a functional description of the software watchdog timer (WDT) unit, including a state diagram, block diagram, and discussion of modes of operation. 5.3.5.1 Software Watchdog Timer Unit The device provides a software watchdog timer feature to prevent system lock in case the software becomes trapped in loops with no controlled exit. Watchdog timer operations are configured in the system watchdog control register (SWCRR).
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System Configuration Although most software disciplines permit or even encourage the watchdog concept, some systems require a selection of time-out periods. For this reason, the software watchdog timer must provide a selectable range for the time-out period. Figure 5-26 shows how to handle this need. SWCRR[SWEN] System Clocking Clock Disable SWCRR[SWPR] 65,536 Divider SWCRR[SWRI] SWSRR[WS] Service SWCNR Time-out 16-Bit Decrementer Event Logic Reload Reset or mcp SWCRR[SWTC] Figure 5-26.
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System Configuration • 5.3.6 According to the value of SWCRR[SWRI], the WDT timer causes a hard reset or machine check interrupt to the core. — Reset mode (SWCRR[SWRI] = 1). Software watchdog timer causes a hard reset (this is the default value after hard reset). — Interrupt mode (SWCRR[SWRI] = 0). Software watchdog timer causes a machine check interrupt to the core.
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System Configuration register (RTCTR) is used to enable or disable the various timer functions. The real time counter event register (RTEVR) is used to report the interrupt source. The RTC counter is initialized by software and can be disabled if needed. Figure 5-27 shows the RTC block diagram. RTC Input Clock Real Time Clock Module Second Interrupt Alarm Interrupt CSB Bus Clock Register Interface Figure 5-27. RTC Block Diagram 5.4.
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System Configuration 5.4.5 External Signal Description Table 5-54 lists the external signals for the RTC module. Table 5-37. RTC External Signals Signal I/O RTC_PIT_CLOCK I Description This signal is used as the timebase for the real time clock module. State Meaning — Timing 32.768 KHz typical Requirements — Reset State Always input 5.4.6 RTC Memory Map/Register Definition The RTC programmable register map occupies 32 bytes of memory-mapped space.
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System Configuration 5.4.6.1 Real Time Counter Control Register (RTCNR) The real time counter control register (RTCNR), shown in Figure 5-28, is used to enable RTC functions. The register can be read at any time. Offset 0x00 Access: Read/Write 0 23 R — W Reset 24 25 26 CLEN CLIN 29 — 30 31 AIM SIM All zeros Figure 5-28. Real Time Counter Control Register (RTCNR) Table 5-39 lists the bit fields of RTCNR. Table 5-39.
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System Configuration 5.4.6.2 Real Time Counter Load Register (RTLDR) The real time counter load register (RTLDR), shown in Figure 5-29, contains the 32-bit value to be loaded in the 32-bit RTC counter. Offset 0x04 Access: Read/Write 0 31 R CLDV W Reset All zeros Figure 5-29. Real Time Counter Load Register (RTLDR) Table 5-40 lists the bit field of RTLDR. Table 5-40. RTLDR Bit Settings Bits Name 0–31 CLDV 5.4.6.3 Description Contains the 32-bit value to be loaded in the 32-bit RTC counter.
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System Configuration 5.4.6.4 Real Time Counter Register (RTCTR) The real time counter register (RTCTR), shown in Figure 5-31, is a read-only register that shows the current value in the RTC counter. The CNTV value is not affected by reads or writes to RTCTR. Offset 0x0C Access: Read only 0 31 R CNTV W Reset All zeros Figure 5-31. Real Time Counter Register (RTCTR) Table 5-42 lists the bit field of RTCTR. Table 5-42. RTCTR Bit Settings Bits Name 0–31 CNTV RTC counter value field.
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System Configuration 5.4.6.6 Real Time Counter Alarm Register (RTALR) The real time counter alarm register (RTALR), shown in Figure 5-33, contains the 32-bit alarm (ALRM) value. When the value of the RTC counter equals the RTALR[ALRM] value, a maskable interrupt is generated. Offset 0x14 Access: Read/Write 0 31 R ALRM W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 5-33.
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System Configuration RTCNR[SIM] RTCNR[CLIN] RTPSR[PRSC] Second Interrupt RTLDR[CLDV] RTEVR[SIF] RTC Input System Bus Clock Clock Disable 32-bit Prescaler RTCNR[CLEN] 32-bit Counter RTCTR[CNTV] = RTEVR[AIF] Alarm Interrupt RTCNR[AIM] RTALR[ALRM] Figure 5-34. Real Time Clock Module Functional Block Diagram 5.4.7.2 RTC Operational Modes The RTC unit can operate in the following modes: • RTC enable/disable mode RTCNR[CLEN] enables the RTC timer.
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System Configuration — RTC uses the internal input clock mode (RTCNR[CLIN] = 0) — RTC uses the external RTC_PIT_CLOCK (RTCNR[CLIN] = 1) 5.4.8 RTC Reset Sequence The RTC is not reset automatically on POR or HRESET. • To assert reset to the RTC, program RTCCR[RESET_RTC] to 1. • To deassert reset to the RTC, program RTCCR[RESET_RTC] to 0. 5.4.9 RTC Initialization Sequence The recommended initialization sequence for the RTC is as follows: 1. Write to RTPSR to set the RTC prescaler to the desired value 2.
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System Configuration Figure 5-35 shows the functional PIT block diagram. PIT Clock Periodic Interrupt Periodic Interval Timer System Clock Register Interface Figure 5-35. Periodic Interval Timer High Level Block Diagram 5.5.
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System Configuration 5.5.5 PIT Memory Map/Register Definition The PIT programmable register map occupies 32 bytes of memory-mapped space. Reading undefined portions of the memory map returns all zeros; writing has no effect. All PIT registers are 32 bits wide and reside on 32-bit address boundaries and should only be accessed as 32-bit quantities. All addresses used in this chapter are offsets from PIT base, as defined in Chapter 3, “Memory Map.” Table 5-47 shows the PIT memory map. Table 5-47.
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System Configuration Table 5-48. PTCNR Bit Settings (continued) Bits Name 25 CLIN 26–30 — 31 PIM 5.5.5.2 Description Input clock control bit. The input clock to the PIT can be either an internal system clock or an external RTC_PIT_CLOCK. 0 The input clock to the periodic interrupt timer is internal system clock. 1 The input clock to the periodic interrupt timer is external RTC_PIT_CLOCK. Write reserved, read = 0 Periodic interrupt mask bit.
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System Configuration Table 5-50 defines the bit fields of PTPSR. Table 5-50. PTPSR Bit Settings Bits Name 0–31 PRSC PIT prescaler bits. Selects the input clock divider to generate the PIT counter clock. The prescaler is programmed to divide the PIT clock input by values from 1 to 4,294,967,296. The value 0x0000 divides the clock by 1 and 0xFFFF_FFFF divides the clock by 4,294,967,296. To accurately predict the timing of the next count, change the PRSC bit only when the enable bit PTCNR[CLE] is clear.
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System Configuration Table 5-52 defines the bit fields of PTEVR. Table 5-52. PTEVR Bit Settings Bits Name 0–30 — Write reserved, read = 0 31 PIF Periodic interrupt flag bit. It is asserted after the SPMPIT counter counts to zero. This status bit should be cleared by software. 5.5.6 Description Functional Description This section provides a functional description of the PIT unit, including a block diagram and discussion of operational modes. 5.5.6.
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System Configuration • • 5.5.7 The PTCNR[CLEN] bit enables the PIT timer. It should be set by software after a system reset to enable the PIT timer. — PIT disable mode (PTCNR[CLEN] = 0). When the PIT’s clock is disabled, counter maintains its old value. — PIT enable mode (PTCNR[CLEN] = 1). When the counter’s clock is enabled, it continues counting using the previous value. PIT periodic interrupt enable/disable mode: — PIT periodic interrupt enable mode (PTCNR[PIM] = 1).
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System Configuration Figure 5-42 shows the functional GTM block diagram. Global Configuration Register 1 GTEVR1 Event Register GTPSR1 Prescale Register GTMDR1 Mode Register Divider GTCNR1 16-Bit Counter GTRFR1 Reference Register GTCPR1 Capture Register General System Clock Timer Clock Generator clock Synchronizer GTCFR1 GTCFR2 TGATE1 TGATE2 TGATE3 TGATE4 TIN1 TIN2 TIN3 TIN4 Capture Detection TOUT4 TOUT3 TOUT2 TOUT1 Timer1 Timer2 Timer3 Timer4 Registers Interface Figure 5-42.
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System Configuration • • • • Input capture capability Output compare with programmable mode for the output pin Free run and restart modes Functional and programming compatibility with MPC8260 timers 5.6.3 GTM Modes of Operation The GTM unit can operate in the following modes: • Cascaded modes • Clock source modes • Reference modes • Capture modes 5.6.3.
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System Configuration • Reset reference mode. The corresponding timer count is reset immediately after the reference value is reached. 5.6.3.4 Capture Modes Each timer has a 16-bit field in GTCPR, used to latch the value of the counter when a defined transition of TINx is sensed by the corresponding input capture edge detector. • Normal gate mode enables the count on a falling edge of the TGATE pin and disables the count on the rising edge of TGATE.
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System Configuration Table 5-54 provides detailed descriptions of the external GTM signals. Table 5-54. GTM External Signals—Detailed Signal Descriptions Signal I/O Description TINn I Global timer capture control signal. Used to latch the value of the counter when a defined transition of TINn is sensed by the corresponding input capture edge detector. State Asserted/Negated —According to the programmed polarity by the corresponding Meaning GTMDRn[CE]).
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System Configuration Table 5-55 shows the memory map of the GTM. Table 5-55. GTM Register Address Map Offset Register Access Reset Value Section/ Page General Purpose (Global) Timer Module 1—Block Base Address 0x0_0500 0x000 0x001–0x003 0x004 0x005–0x00F Timer 1 and 2 global timers configuration register (GTCFR1) 0x0000 5.6.5.1/5-58 — — — R/W 0x0000 5.6.5.1/5-58 — — — R/W 0x0000 5.6.5.2/5-62 R/W 0xFFFF 5.6.5.3/5-63 R/W 0x0000 5.6.5.4/5-63 R/W 0x0000 5.6.5.
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System Configuration and resetting of a pair of timers (1 and 2 or 3 and 4) or of a groups of timers (1, 2, 3, and 4) if one bus cycle is used. GTCFR is cleared by reset. NOTE For proper operation of the timers, do not change the modes of operation and enable the timer in the same register write operation. The modes can be changed when GTCFRn[RSTn] is cleared. However, when GTCFRn[RSTn] are set, they are the only bits that can be changed.
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System Configuration Table 5-56. GTCFR1 Bit Settings (continued) Bits Name Description 5 GM1 Gate mode for TGATE1 0 Restart gate mode. The TGATE1 is used to enable/disable count. A low level of TGATE1 enables and a falling edge of TGATE1 restarts the count (reset the dynamic counter’s count value to 0) and a high level of TGATE1 disables the count. 1 Normal gate mode. This mode is the same as 0, except the falling edge of TGATE1 does not restart the appropriate count value in GTCNR1[CNV1].
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System Configuration Table 5-57 defines the bit fields of GTCFR2. Table 5-57. GTCFR2 Bit Settings Bits Name Description 0 PCAS Pair-cascade mode 0 Normal operation. 1 Timers 3 and 4 cascade to form a 32-bit timer. Note: This bit is ignored in super-cascade mode (GTCFR2[SCAS] = 1). Note: It is allowed to change the value of this bit only when the corresponding timers are in reset mode.
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System Configuration 5.6.5.2 Global Timers Mode Registers (GTMDR1–GTMDR4) The global timers mode registers (GTMDR1, GTMDR2, GTMDR3, and GTMDR4) are shown in Figure 5-45. Erratic behavior may occur if GTCFR1 and GTCFR2 are not initialized before the GTMDRn. Only GTCFRn[RSTn] and GTCFRn[STPn] can be modified at any time. 0x10(GTMDR1) 0x12(GTMDR2) Offset 0x20(GTMDR3) 0x22(GTMDR4) 0 R Access: Read/Write 7 8 SPS W 9 CE Reset 10 11 12 OM ORI FRR 13 14 ICLK 15 GE All zeros Figure 5-45.
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System Configuration Table 5-58. GTMDR Bit Settings (continued) Bits Name Description 13–14 ICLK Input clock source for the timer. 00 Internally cascaded input. This selection means: For ICLK1, the timer 1 input is the output of timer 2. For ICLK2, the timer 1 input is the output of timer 2, the timer 2 input is the output of timer 3, the timer 3 input is the output of timer 4. For ICLK3, the timer 3 input is the output of timer 4.
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System Configuration Table 5-60 defines the bit fields of GTCPRn. Table 5-60. GTCPRn Bit Settings Bits Name 0–15 LCV 5.6.5.5 Description Latched counter value. Corresponding timer’s 16-bit latched value. Global Timers Counter Registers (GTCNR1–GTCNR4) Global timers counter registers (GTCNR1, GTCNR2, GTCNR3, and GTCNR4), shown in Figure 5-48, are four 16-bit, memory-mapped, read/write up-counters.
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System Configuration Table 5-62 defines the bit fields of GTEVRn. Table 5-62. GTEVRn Bit Settings Bits Name 0–13 — 14 REF Output reference event 0 No event 1 The counter reached the GTRFRn[TRV] value. GTMDRn[ORI] is used to enable the interrupt request caused by this event. 15 CAP Counter capture event Corresponding timer’s 16-bit read/write up-counter value. 0 No event 1 The counter value has been latched into the GTCPRn[LCV]. GTMDRn[CE] is used to enable generation of this event. 5.6.5.
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System Configuration 5.6.6 Functional Description This section provides a functional description of the general-purpose timer units, including detailed description of its modes of operation. 5.6.6.1 General-Purpose Timer Units The clock input to the timer’s prescaler can be selected from the following sources: • The system clock • The system slow go clock (internally divided by 16) The general system clock is generated in the clock synthesizer and defaults to the system frequency.
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System Configuration triggering the capture is selected by the corresponding GTMDRn[CE] bits. Upon a capture or reference event, corresponding GTEVRn[REF] or GTEVRn[CAP] is set and a maskable interrupt request is issued to the interrupt controller. • Normal gate mode enables the count on a falling edge of TGATE and disables the count on the rising edge of TGATE. This mode allows the timer to count conditionally, based on the state of TGATE.
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System Configuration In this mode, two 16-bit timers can be internally cascaded to form a 32-bit counter: timer 1 may be internally cascaded to timer 2 and timer 3 may be internally cascaded to timer 4, as shown in Figure 5-52. Since the decision to cascade timers is made independently, the user has the option of selecting two 16-bit timers and one 32-bit timer (GTCFR1[PCAS] = 1, GTCFR2[PCAS] = 0 or GTCFR1[PCAS1] = 0, GTCFR2[PCAS] = 1), or two 32-bit timers (GTCFR1[PCAS] = 1 and GTCFR2[PCAS] = 1).
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System Configuration 5.6.7 Initialization/Application Information (Programming Guidelines for GTM Registers) The following initialization sequence of GTM is recommended: • Write to GTCFRn in order to reset, to stop, or to configure the appropriate timer’s operation: cascaded timers configuration, gate mode configuration. • Write to GTPSRn[PPS] fields in order to program the appropriate timer’s clock primary prescaler.
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System Configuration 5.7.1 External Signal Description Table 5-64 describes the power management signals. Table 5-64. System Control Signals—Detailed Signal Descriptions Signal I/O QUIESCE O Description Quiesce state. Indicates that the processor system and e300 core are in low- power state. State Asserted—The system and e300 core are in low-power state. Meaning Negated—The system and e300 core are not in low-power state.
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System Configuration Table 5-66 defines the bit fields of PMCCR. ‘ Table 5-66. PMCCR Bit Settings Bits Name 0–29 — 30 DLPEN DDR SDRAM low power enable 0 The DDR SDRAM memory controller is prevented from entering low-power state. 1 The DDR SDRAM memory controller enters low-power state when the rest of the system enters low-power, according to SLPEN setting. DDR SDRAM enters self-refresh mode (if enabled by DDR_SDRAM_CFG[SREN] memory controller register) and DDR clocks (MCKn) are shut off.
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System Configuration Table 5-67. Software-Controller Power-Down States—Basic Description (continued) Core Mode System Mode Low Power (PMCCR[SLPEN] = 1) 5.7.3.1 Nap Sleep Core Responds To Description Core operation as described above. System is in idle state, DDR SDRAM memory operates in self-refresh mode if enabled. Snoop Interrupt No Yes DDR SDRAM State Quiesce Signal State According to PMCCR [DLPEN] Asserted Shutting Down Clocks to Unused Blocks As described in Section 4.5.2.
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System Configuration 5.7.3.3 Exiting Core and System Low-Power States The device can exit low-power state and return to full-on mode for one of the following reasons: • The core internal time base unit invokes a request to exit low-power state. • The power management controller has detected that the system is not idle and there are outstanding transactions on the internal bus. The actions taken to exit low-power state depend on the mode and whether the system or only the core are in this state.
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System Configuration MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev.
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Chapter 6 Arbiter and Bus Monitor This chapter describes operation theory of the arbiter in the device. In addition, it describes configuration, control, and status registers of the arbiter. 6.1 Overview The arbiter is responsible for providing coherent system bus arbitration. It tracks all address and data tenures and provides all the arbitration signals to masters and slaves. In addition, it monitors the bus and reports on errors and protocol violations.
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Arbiter and Bus Monitor consecutive transactions can be limited by programming arbiter configuration register. See Section 6.2.1, “Arbiter Configuration Register (ACR),” for more details. NOTE Write accesses to different interfaces are not guaranteed to finish in order. 6.2 Arbiter Memory Map/Register Definition Table 6-1 shows the memory map for arbiter’s configuration, control, and status registers. Table 6-1.
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Arbiter and Bus Monitor 6.2.1 Arbiter Configuration Register (ACR) The arbiter configuration register (ACR) defines the arbiter modes and parked master on the bus. Figure 6-1 shows the fields of ACR.
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Arbiter and Bus Monitor Table 6-2. ACR Field Descriptions (continued) Bits Name 21–23 RPTCNT 24–25 — 26–27 APARK Address parking. Specifies arbiter bus parking mode. 00 Park to master. Arbiter parks the address bus to the master, that is selected by numeric value of PARKM field. 01 Park to last owner. Arbiter parks the address bus to last bus owner. 10 Disable. Arbiter does not assert BG to any master, if no BR is present. 11 Reserved 28–31 PARKM Parking master.
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Arbiter and Bus Monitor Table 6-3 describes ATR fields. Table 6-3. ATR Field Descriptions Bits Name Description 0–15 DTO Data time out. Specifies the time-out period for the data tenure. The granularity of this field is128 bus clocks. The maximum value is 8355840 coherent system bus clocks. Data time_out occurs if the data tenure does not end before the specified time-out period. When DTO = n, the timeout cycle is n  128.
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Arbiter and Bus Monitor Table 6-4. AEER Bit Settings Bits Name Description 27 RES Reserved transfer type. Specifies, whether transaction with reserved transfer type will be reported in arbiter event registers. 0 Reserved transaction isn’t reported in arbiter event registers. 1 Reserved transaction is reported in arbiter event registers. 28 ECW External Control Word transfer type. Specifies, whether transaction with external control word transfer type will be reported in arbiter event registers.
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Arbiter and Bus Monitor Table 6-5. AER Field Descriptions (continued) Bits Name 27 RES Reserved transfer type. Reports on transaction with reserved transfer type. See Section 6.3.2.5, “Reserved Transaction Type,” for more information. 0 No transaction with reserved transfer type occurred. 1 Transaction with reserved transfer type occurred. 28 ECW External control word transfer type. Reports on transaction with external control word transfer type. See Section 6.3.2.
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Arbiter and Bus Monitor Table 6-6. AIDR Field Descriptions (continued) Bits Name Description 28 ECW External control word transfer type. Transaction with external control word transfer type interrupt definition. 0 Transaction with external control word transfer type causes regular interrupt. 1 Transaction with external control word transfer type causes MCP interrupt. 29 AO 30 DTO Data time out. Data tenure time out interrupt definition. 0 Data tenure time out causes regular interrupt.
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Arbiter and Bus Monitor Table 6-7. AMR Field Descriptions (continued) Bits Name 30 DTO Data time out. Data tenure time out interrupt mask bit. 0 Data tenure time out interrupt disabled. 1 Data tenure time out interrupt enabled. 31 ATO Address time out. Address tenure time out interrupt mask bit. 0 Address tenure time out interrupt disabled. 1 Address tenure time out interrupt enabled. 6.2.
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Arbiter and Bus Monitor Table 6-8. AEATR Field Descriptions (continued) Bits 11–15 Name Description MSTR_ID Master ID. 00000 e300 core data transaction 00001 Reserved 00010 e300 core instruction fetch 00011 Reserved 00100 TSEC1 00101 TSEC2 00110 Reserved 00111 USB 01000 Reserved 01001 I2C (boot sequencer) 01010 JTAG 01011 Reserved 01100 eSDHC 01101–11100 Reserved 11101 PCI Express 11110 Reserved 11111 DMA Note: Master ID reflects the source of transaction and is used for debug purpose.
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Arbiter and Bus Monitor failure had caused a deadlock situation. For more information, see Section 6.4.2, “Error Handling Sequence.” Figure 6-8 shows the fields of AEADR. Offset 0x1C Access: Read only 0 31 R ADDR W Reset All zeros Figure 6-8. Arbiter Event Address Register (AEADR) Table 6-9 describes AEADR fields. Table 6-9. AEADR Field Descriptions Bits Name 0–31 ADDR 6.2.9 Description Address of the event reported in AEATR register. See Section 6.2.
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Arbiter and Bus Monitor Table 6-10. AERR Field Descriptions Bits Name 28 ECW 29 AO 30 DTO Data time out. Data tenure time out interrupt definition. 0 Data tenure time out causes interrupt. 1 Data tenure time out causes reset request. 31 ATO Address time out. Address tenure time out interrupt definition. 0 Address tenure time out causes interrupt. 1 Address tenure time out causes reset request. 6.3 Description External control word transfer type.
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Arbiter and Bus Monitor A master has to acquire address bus ownership before it starts any transaction. The master asserts its own bus request signal along with the arbitration attribute signals REPEAT and PRIORITY[0:1]. The arbiter later asserts the corresponding address bus grant signal to the requesting master depending on the system states and arbitration scheme. See Section 6.3.1.1, “Address Bus Arbitration with PRIORITY[0:1],” for details on arbitration scheme.
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Arbiter and Bus Monitor M6 Z M6 Z ... M6 M4 M6 M5 M6 M0 M6 M4 M6 M5 M6 M3 M6 M4 M6 M5 M6 M1 M6 M4 M6 M5 M6 M0 M6 M4 M6 M5 M6 M3 M6 M4 M6 M5 M6 M2 ... Level 3 Z M6 M4 M5 Y M4 M5 Y ... Level 2 M4 M5 M0 M4 M5 M3 M4 M5 M1 M4 M5 M0 M4 M5 M3 M4 M5 M2 ... Y M4 M5 M0 M3 X M0 M3 X ... Level 1 M0 M3 M1 M0 M3 M2 M0 M3 M1 ... X M3 M0 Level 0 M1 M1 M2 M1 M2 ... M2 Figure 6-11. An Example of Priority-Based Arbitration Algorithm NOTE See each bus master’s chapter and Section 5.2.2.
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Arbiter and Bus Monitor completion of snoop copyback, the arbiter grants the bus back to the master that had its transaction ARTRYed. 6.3.1.4 Address Bus Parking The arbiter supports address bus parking. This feature implies that when no master is requesting the bus (all bus requests are negated), the arbiter can choose to park the address bus (or assert the address bus grant) to a master. The parked master can skip the bus request and assume the bus mastership directly.
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Arbiter and Bus Monitor 6.3.2.2 Data Time Out Data time out occurs, if the data tenure was not ended before the specified time-out period (programmed by ATR[DTO]). In this case, the arbiter performs as follows: 1. Ends the data tenure by asserting transfer error. 2. Reports on this event in AER[DTO]. 3. Issues reset request, MCP or regular interrupt according to AERR[DTO] and AIDR[DTO], if enabled by AMR[DTO]. 4. Updates transaction attributes and address of AEATR and AEADR for the first error event. 6.
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Arbiter and Bus Monitor 4. Updates transaction attributes and address of AEATR and AEADR for the first error event. 6.3.2.5 Reserved Transaction Type Table 6-12 shows transaction types defined as reserved. Table 6-12.
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Arbiter and Bus Monitor • • 6.4 Section 6.2.8, “Arbiter Event Address Register (AEADR)” Section 6.2.9, “Arbiter Event Response Register (AERR)” Initialization/Applications Information The following sections describe the initialization and error handling sequences for the arbiter. 6.4.1 Initialization Sequence The following initialization sequence is recommended: 1. Write to ACR to configure pipeline depth, address bus parking mode, global maximum repeat count. 2.
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Chapter 7 e300 Processor Core Overview This chapter provides an overview of features for the embedded microprocessors in the e300 core family, which are PowerPC microprocessors built on Power Architecture technology. Throughout this chapter, the terms ‘e300 core’, ‘core’, and ‘processor’ are used interchangeably. The term, ’e300c3’ is used when describing an implementation-specific feature or when a difference exists between different configurations.
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e300 Processor Core Overview Figure 7-1 shows a block diagram of the e300c3 core. Note that the e300c3 supports floating-point operations and includes two integer units.
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e300 Processor Core Overview The e300c3 includes 16-Kbyte, four way set-associative instruction and data caches. The MMUs contain 64-entry, two-way, set-associative, data and instruction translation lookaside buffers (DTLB and ITLB) that provide support for demand-paged, virtual-memory, address translation, and variable-sized block translation. The TLBs use a least recently used (LRU) replacement algorithm and the caches use a pseudo least recently used algorithm (PLRU).
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e300 Processor Core Overview • • • Independent execution units and two register files — Branch processing unit (BPU) featuring static branch prediction — Two 32-bit integer units (IU) in the e300c3 — FPU based on the IEEE Std 754™ for both single- and double-precision operations — Load/store unit (LSU) for data transfer between data-cache and general-purpose registers (GPRs) and floating-point registers (FPRs) — System register unit (SRU) that executes condition register (CR), special-purpose register (
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e300 Processor Core Overview • • Integrated power management — Internal processor/bus clock multiplier ratios — Three power-saving modes: doze, nap, and sleep — Automatic dynamic power reduction when internal functional units are idle In-system testability and debugging features through JTAG boundary-scan capability Features specific to the e300 core not present on the G2 processors follow: • Enhancements to the register set — The e300 core has one more HID0 bit than the G2: – The enable cache parity ch
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e300 Processor Core Overview • Debug features — Breakpoint status recorded in DBCR and IBCR control registers — Two signals for the debug interface: stopped and ext_halt — Performance monitor registers for system analysis in the e300c3 Figure 7-1 provides a block diagram of the e300 core that shows how the execution units—IU, FPU, BPU, LSU, and SRU—operate independently and in parallel.
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e300 Processor Core Overview 7.1.2.2 Branch Processing Unit (BPU) The BPU receives branch instructions from the fetch unit and performs CR lookahead operations on conditional branches to resolve them early, achieving the effect of a zero-cycle branch in many cases. The BPU uses a bit in the instruction encoding to predict the direction of the conditional branch.
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e300 Processor Core Overview 7.1.3.3 Load/Store Unit (LSU) The LSU executes all load and store instructions and provides the data transfer interface between the GPRs, FPRs, and the cache/memory subsystem. The LSU calculates effective addresses, performs data alignment, and provides sequencing for load/store string and multiple instructions. Load and store instructions are issued and executed in program order; however, the memory accesses can occur out of order.
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e300 Processor Core Overview 7.1.5.1 Memory Management Units (MMUs) The core MMUs support up to 4 Petabytes (252) of virtual memory and 4 Gigabytes (232) of physical memory (referred to as real memory in the architecture specification) for instruction and data. The MMUs also control access privileges for these spaces on block and page granularities. Referenced and changed status is maintained by the processor for each page to assist implementation of a demand-paged virtual memory system.
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e300 Processor Core Overview For more information about memory management for the core, see Section 7.4.5.2, “Implementation-Specific Memory Management.” 7.1.5.2 Cache Units The e300c3 provides 16-Kbyte, four-way set-associative instruction and data caches. The cache block is 32 bytes long. The caches adhere to a write-back policy, but the e300 core allows control of cacheability, write policy, and memory coherency at the page and block levels. The caches use a pseudo LRU replacement policy.
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e300 Processor Core Overview noncacheable access is performed), and provides support for a write operation to proceed a previously queued read data tenure (for example, allowing a snoop push to be enveloped by the address and data tenures of a read operation). Because the processor can dynamically optimize run-time ordering of load/store traffic, overall performance is improved. 7.1.
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e300 Processor Core Overview 7.1.7.2 Time Base/Decrementer The time base is a 64-bit register (accessed as two 32-bit registers) that is incremented once every four bus clock cycles; external control of the time base is provided through the time base/decrementer clock base enable (tben) signal. The decrementer is a 32-bit register that generates a decrementer interrupt after a programmable delay.
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e300 Processor Core Overview • — The performance monitor counter registers (PMC0–PMC3) are 32-bit counters used to count software-selectable events. Each counter counts up to 128 events. UPMC0–UPMC3 provide user-level read access to these registers. They are identified in Table 7-2. — The performance monitor global control register (PMGC0) controls the counting of performance monitor events. It takes priority over all other performance monitor control registers.
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e300 Processor Core Overview 7.4 Implementation-Specific Information This section describes the PowerPC architecture in general and specific details about the implementation of the e300 core as a low-power, 32-bit member of this PowerPC core family. The main topics addressed are as follows: • Section 7.4.1, “Register Model,” describes the registers for the operating environment architecture common among e300 cores that implement the PowerPC architecture and describes the programming model.
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e300 Processor Core Overview Having access to privileged instructions, registers, and other resources allows the operating system to control the application environment (providing virtual memory and protecting operating system and critical machine resources). Instructions that control the state of the e300 core, the address translation mechanism, and supervisor registers can be executed only when the core is operating in supervisor mode.
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e300 Processor Core Overview SUPERVISOR MODEL Configuration Registers Hardware Implementation Registers USER MODEL General-Purpose Registers (32-Bit) Machine State Register MSR HID0 1 SPR 1008 GPR0 HID1 1 SPR 1009 GPR1 HID2 1 SPR 1011 Instruction BAT Registers GPR31 Memory Base Address Register MBAR 1 Data BAT Registers DBAT0U SPR 536 IBAT0L SPR 529 DBAT0L SPR 537 IBAT1U SPR 530 DBAT1U SPR 538 FPR0 IBAT1L SPR 531 DBAT1L SPR 539 FPR1 IBAT2U SPR 532 DBAT2U SPR 540 IBAT2L SPR
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e300 Processor Core Overview The following sections describe the e300 core-implementation-specific features as they apply to registers. 7.4.1.1 UISA Registers UISA registers are user-level registers that include the following. 7.4.1.1.1 General-Purpose Registers (GPRs) The PowerPC architecture defines 32 user-level GPRs that are 32 bits wide in 32-bit cores. The GPRs serve as the data source or destination for all integer instructions. 7.4.1.1.
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e300 Processor Core Overview • XER register The 32-bit XER contains the summary overflow bit, integer carry bit, overflow bit, and a field specifying the number of bytes to be transferred by a Load String Word Indexed (lswx) or Store String Word Indexed (stswx) instruction. 7.4.1.2 VEA Registers The VEA introduces the time base facility (TB) for reading. The TB is a 64-bit register pair whose contents are incremented once every four core input clock cycles.
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e300 Processor Core Overview Table 7-2. MSR Bit Descriptions (continued) Bits Name 16 EE External interrupt enable 0 The processor ignores external interrupts, system management interrupts, and decrementer interrupts. 1 The processor is enabled to take an external interrupt, system management interrupt, or decrementer interrupt.
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e300 Processor Core Overview Table 7-2. MSR Bit Descriptions (continued) 1 Bits Name Description 30 RI Recoverable interrupt (for system reset and machine check interrupts) 0 Interrupt is not recoverable 1 Interrupt is recoverable 31 LE Little-endian mode enable 0 The processor runs in big-endian mode 1 The processor runs in little-endian mode. All reserved bits should be set to zero for future compatibility. 7.4.1.3.
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e300 Processor Core Overview • • • The time base register (TB) is a 64-bit register that maintains the time of day and operates interval timers. It consists of two 32-bit fields: time base upper (TBU) and time base lower (TBL). The processor version register (PVR) is a read-only register that identifies the version (model) and revision level of the processor. See Table 7-9 for the version and revision level of the PVR for the e300 processor core.
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e300 Processor Core Overview Table 7-3 shows the bit definitions for HID0. Table 7-3. e300 HID0 Bit Descriptions Bits Name Function 0 EMCP Enable mcp. The purpose of this bit is to mask out machine check interrupts caused by assertion of mcp, similar to how MSR[EE] can mask external interrupts. 0 Masks mcp. Asserting mcp does not generate a machine check interrupt or a checkstop.
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e300 Processor Core Overview Table 7-3. e300 HID0 Bit Descriptions (continued) Bits Name Function 11 DPM 12–15 — 16 ICE Instruction cache enable 0 The instruction cache is neither accessed nor updated. All pages are accessed as if they were marked cache-inhibited (WIM = x1x). Potential cache accesses from the bus (snoop and cache operations) are ignored.
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e300 Processor Core Overview Table 7-3. e300 HID0 Bit Descriptions (continued) Bits Name Function 21 DCFI Data cache Flash invalidate 0 The data cache is not invalidated. The bit is cleared when the invalidation operation begins (usually the next cycle after the write operation to the register). The data cache must be enabled for the invalidation to occur. 1 An invalidate operation is issued that marks the state of each data cache block as invalid without writing back modified cache blocks to memory.
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e300 Processor Core Overview Table 7-5 shows the bit definitions for HID1 Table 7-5.
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e300 Processor Core Overview Table 7-6. e300HID2 Bit Descriptions (continued) Bits Name 11 ELRW Enable weighted LRU. This bit enables the use of an adjusted (weighted) LRU. 0 Normal operation. 1 The dcbt, dcbtst, and dcbz instructions use and adjusted (weighted) LRU such that they always select and replace the lowest unlocked way in the data cache. 12 NOKS No kill for snoop. This bit enables the forcing of kill-type snoops to flush data instead of killing it. 0 Normal operation.
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e300 Processor Core Overview 7.4.2.1 PowerPC Instruction Set and Addressing Modes All PowerPC instructions are encoded as single-word (32-bit) opcodes. Instruction formats are consistent among all instruction types, permitting efficient decoding to occur in parallel with operand accesses. This fixed instruction length and consistent format simplifies instruction pipelining.
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e300 Processor Core Overview — User-level cache instructions — Segment register manipulation instructions The e300 core implements the following instructions defined as optional by the PowerPC architecture: — Floating Select (fsel) — Floating Reciprocal Estimate Single-Precision (fres) — Floating Reciprocal Square Root Estimate (frsqrte) — Store Floating-Point as Integer Word (stfiwx) Note that this grouping of instructions does not indicate the execution unit that executes a particular instruction or grou
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e300 Processor Core Overview 7.4.3 Cache Implementation The following sections describe the general cache characteristics as implemented in the PowerPC architecture and the core implementation. 7.4.3.1 PowerPC Cache Characteristics The PowerPC architecture does not define hardware aspects of cache implementations.
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e300 Processor Core Overview The e300c3 data cache is configured as 128 sets of four blocks per set. The organization of the data cache is shown in Figure 7-3. 128 Sets Block 0 Address Tag 0 State Words [0–7] Block 1 Address Tag 1 State Words [0–7] Block 2 Address Tag 2 State Words [0–7] Block 3 Address Tag 3 State Words [0–7] 8 Words/Block Figure 7-3.
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e300 Processor Core Overview Cache coherency is enforced by on-chip bus snooping logic. Because the e300 core data cache tags are single-ported, a simultaneous load/store and snoop access represents a resource contention. The snoop access is given first access to the tags. The load or store then occurs on the clock following the snoop. Parity is now integrated into both instruction and data cache memory. A machine check interrupt is now taken upon the detection of an instruction or data cache parity error.
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e300 Processor Core Overview To prevent the program state from being lost due to a system reset, a machine check interrupt or an instruction-caused interrupt in the interrupt handler should save the information stored in SRR0 and SRR1 early and before enabling external interrupts. The PowerPC architecture supports four types of interrupts: • Synchronous, precise These are caused by instructions.
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e300 Processor Core Overview the e300 core, are caused by instructions. A system management interrupt is an implementation-specific interrupt. The interrupt classes are shown in Table 7-7. Table 7-7.
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e300 Processor Core Overview Table 7-8. Exceptions and Interrupts (continued) Interrupt Type Vector Offset (hex) Exception Conditions External interrupt 00500 Caused when MSR[EE] = 1 and the int signal is asserted. Alignment 00600 Caused when the core cannot perform a memory access for any of the reasons described below: • The operand of a floating-point load or store instruction is not word-aligned. • The operands of lmw, stmw, lwarx, and stwcx. instructions are not aligned.
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e300 Processor Core Overview Table 7-8. Exceptions and Interrupts (continued) Interrupt Type Vector Offset (hex) Exception Conditions Data store translation miss 01200 Caused when the effective address for a data store operation cannot be translated by the DTLB, or when a DTLB hit occurs and the change bit in the PTE must be set due to a data store operation.
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e300 Processor Core Overview an interim 52-bit virtual address and hashed page tables for generating 32-bit physical addresses. The MMUs in the e300 core rely on the interrupt processing mechanism for the implementation of the paged virtual memory environment and for enforcing protection of designated memory areas. Instruction and data TLBs provide address translation in parallel with the on-chip cache access, incurring no additional time penalty in the event of a TLB hit.
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e300 Processor Core Overview • an internal interrupt, the execution unit reports the interrupt to the completion/write-back pipeline stage and discontinues instruction execution until the interrupt is handled. The interrupt is not signaled until that instruction is the next to be completed. Execution of most floating-point instructions is pipelined within the FPU, allowing up to three instructions to execute in the FPU concurrently. The FPU pipeline stages are multiply, add, and round-convert.
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e300 Processor Core Overview address transfer, transfer attribute, address termination, data arbitration, data transfer, data termination, and core state signals. Test and control signals provide diagnostics for selected internal circuits.
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e300 Processor Core Overview • • • • • These signals include the external interrupt signal (int), critical interrupt signal (cint), checkstop signals, performance monitor signal (pm_event_in) via the PM counters, and both soft reset and hard reset signals. They are used to interrupt and, under various conditions, to reset the core. JTAG/debug interface signals The JTAG (based on the IEEE 1149.
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e300 Processor Core Overview 7.5 Differences Between Cores The e300 core has similar functionality to the G2_LE core. Table 7-9 describes the differences between the G2_LE and the e300. Table 7-9. Differences Between e300 and G2_LE Cores e300 Core G2_LE Core Impact New HID0 bits — The e300 core has a new HID0 bit defined to enable cache parity error reporting (ECPE). New HID1 bits — The e300 core has new HID1 bits defined to extend the number of PLL configuration signals to seven (PC5, PC6).
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e300 Processor Core Overview Table 7-9. Differences Between e300 and G2_LE Cores (continued) e300 Core G2_LE Core Impact Data cache queue sharing — The e300 has a new data cache queue sharing extension that allows the two burst-write queues in the bus unit to be used interchangeably for cache replacements and snoop pushes. Thus, the data cache can support two outstanding cache replacements or two outstanding snoop push operations on the bus at any given time.
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e300 Processor Core Overview MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev.
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Chapter 8 Integrated Programmable Interrupt Controller (IPIC) This chapter describes the integrated programmable interrupt controller (IPIC), including a definition of the external signals and their functions. Also, the configuration, control, and status registers are described in this chapter. Note that individual chapters in this reference manual describe specific initialization aspects for each individual block. 8.
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Integrated Programmable Interrupt Controller (IPIC) critical interrupt exception. The smi signal is the system management interrupt output from the IPIC to the processor core and causes the system management interrupt exception. The machine check exception is caused by the internal mcp signal generated by the IPIC, informing the host processor of error conditions, assertion of the external IRQ0 machine-check request (enabled when SEMSR[SIRQ0] = 1), and other conditions.
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Integrated Programmable Interrupt Controller (IPIC) Figure 8-1 shows the interrupt sources block diagram. DMA Enhanced Three-Speed Ethernet Controller 1 10/100/1000 MAC int 4 DMA Enhanced Three-Speed Ethernet Controller 2 10/100/1000 MAC cint e300 Core smi mcp 4 USB 2.
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Integrated Programmable Interrupt Controller (IPIC) • External and internal non-maskable machine check conditions, signaled by the sources listed in Table 8-23 through mcp The interrupt controller provides the ability to mask each interrupt source. Any source that can be caused by multiple events are also maskable.
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Integrated Programmable Interrupt Controller (IPIC) 8.4 External Signal Description The following sections provide an overview and detailed descriptions of the IPIC signals. 8.4.1 Overview The device has 4 distinct external interrupt request input signals (IRQ0, IRQ1, IRQ2 and IRQ3). The IPIC interface signals are listed in Table 8-1. Table 8-1.
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Integrated Programmable Interrupt Controller (IPIC) Table 8-2. IPIC External Signals—Detailed Signal Descriptions (continued) Signal I/O INTA Description OD Interrupt request out. Active-low, open drain. When the IPIC is programmed in core disable mode, this output reflects the raw interrupts generated by on-chip sources. See Section 8.3, “Modes of Operation” for details. State Asserted—At least one interrupt is currently being signalled to the external system.
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Integrated Programmable Interrupt Controller (IPIC) Table 8-3. IPIC Register Address Map (continued) Offset Register Access Reset Value Section/ Page 0x010 System internal interrupt group A priority register (SIPRR_A) R/W 0x0530_9770 8.5.4/8-14 0x014 System internal interrupt group B priority register (SIPRR_B) R/W 0x0530_9770 8.5.5/8-15 0x018 System internal interrupt group C priority register (SIPRR_C) R/W 0x0530_9770 8.5.
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Integrated Programmable Interrupt Controller (IPIC) 8.5.1 System Global Interrupt Configuration Register (SICFR) SICFR, shown in Figure 8-2, defines the highest priority interrupt and whether interrupts are grouped or spread in the priority table. Offset 0x00 0 Access: Read/write 1 7 8 9 10 11 12 13 14 15 16 21 22 23 24 31 R — HPI — MPSB MPSA — IPSD IPSC IPSB IPSA — HPIT — W Reset All zeros Figure 8-2.
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Integrated Programmable Interrupt Controller (IPIC) Table 8-4. SICFR Field Descriptions (continued) Bits Name 16–21 — 22–23 Description Write ignored, read = 0 HPIT HPI priority position IPIC output interrupt type. Defines which type of IPIC output interrupt signal (int, cint, or smi) asserts its request to the core in the HPI priority position. These bits cannot be changed dynamically.
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Integrated Programmable Interrupt Controller (IPIC) Table 8-5. SIVCR Field Descriptions (continued) Bits Name 6–24 — 25–31 Description Write ignored, read = 0 IVEC Regular interrupt vector. Specifies a 7-bit unique number of the IPIC’s highest priority regular interrupt source, pending to the core. Note that the when a regular interrupt request occurs, SIVCR can be read. If there are multiple regular interrupt sources, SIVCR latches the highest priority regular interrupt.
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Integrated Programmable Interrupt Controller (IPIC) Table 8-6.
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Integrated Programmable Interrupt Controller (IPIC) 8.5.3 System Internal Interrupt Pending Registers (SIPNR_H and SIPNR_L) Each bit in SIPNR_H and SIPNR_L, shown in Figure 8-4 and Figure 8-5, is assigned an internal interrupt source (implemented bits are listed in Table 8-7). When an interrupt request is received, the interrupt controller sets the corresponding SIPNR bit. When a pending interrupt is handled, the user clears the SIPNR bit by clearing the corresponding event register bit.
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Integrated Programmable Interrupt Controller (IPIC) Table 8-7. SIPNR_H/SIFCR_H/SIMSR_H Bit Assignments (continued) Bits Field 30 I2C2 31 SPI Table 8-8 defines the bit fields of SIPNR_H. Table 8-8. SIPNR_H Field Descriptions Bits Name 0–31 Description INTn Each implemented bit (listed in Table 8-7) corresponds to an internal interrupt source. When an interrupt is received, the interrupt controller sets the corresponding SIPNR bit.
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Integrated Programmable Interrupt Controller (IPIC) Table 8-9. SIPNR_L/SIFCR_L/SIMSR_L Bit Assignments (continued) Bits Field 14 GTM1_2 15–16 — 17 MSIR2 18 MSIR3 19 — 20 GTM1_3 21 — 22 MSIR4 23 MSIR5 24 MSIR6 25 MSIR7 26 GTM1_1 27–29 — 30 DMAC Err 31 — Table 8-10 defines the bit fields of SIPNR_L. Table 8-10. SIPNR_L Field Descriptions Bits Name 0–31 Description INTn Each implemented bit (listed in Table 8-9) corresponds to an internal interrupt source.
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Integrated Programmable Interrupt Controller (IPIC) Table 8-11 defines the bit fields of SIPRR_A. Table 8-11. SIPRR_A Field Descriptions Bits Name Description 0–2 SYSA0P SYSA0 priority order. Defines which interrupt source asserts its request in the SYSA0 priority position. The user should not program the same code to multiple priority positions (0–7). These bits can be changed dynamically. The definition of SYSA0P is as follows: 000 TSEC1 Tx asserts its request in the SYSA0 position.
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Integrated Programmable Interrupt Controller (IPIC) 8.5.6 System Internal Interrupt Group C Priority Register (SIPRR_C) The system internal interrupt group C priority register (SIPRR_C), shown in Figure 8-8, defines the priority between internal interrupt signals. For more information about interrupt priorities, see Section 8.6.3, “Internal Interrupts Group Relative Priority.
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Integrated Programmable Interrupt Controller (IPIC) Table 8-14 defines the bit fields of SIPRR_D. Table 8-14. SIPRR_D Field Descriptions Bits Name 0–2 SYSD0P 3–11, 16–27 SYSD1P–SYSD7P 12–15, 28–31 — 8.5.8 Description SYSD0 priority order. Defines which interrupt source asserts its request in the SYSD0 priority position. The user should not program the same code to more than one priority position (0–7). These bits can be changed dynamically.
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Integrated Programmable Interrupt Controller (IPIC) Table 8-15 defines the bit fields of SIMSR_H. Table 8-15. SIMSR_H Field Descriptions Bits Name 0–31 Description INTn Each implemented bit (listed in Table 8-7) corresponds to an external interrupt source. The user masks an interrupt by clearing the corresponding SIMSR bit. An interrupt is unmasked (enable) by setting the corresponding SIMSR bit. The SIMSR can be read by the user at any time.
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Integrated Programmable Interrupt Controller (IPIC) Note that in core disabled mode the user should use the int output interrupt type (should not use cint or smi output interrupt types) to read an updated SIVCR. Offset 0x28 0 Access: Read write 1 2 3 4 7 8 9 10 11 12 15 16 17 18 19 20 23 24 25 26 27 28 31 R SYSD0T SYSD1T — SYSC0T SYSC1T — SYSB0T SYSB1T — SYSA0T SYSA1T — W Reset All zeros Figure 8-12.
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Integrated Programmable Interrupt Controller (IPIC) Table 8-17. SICNR Field Descriptions (continued) Bits Name Description 24–25 SYSA0T SYSA0 priority position IPIC output interrupt type. Defines which type of the IPIC output interrupt signal (int, smi, or cint) asserts its request to the core in the SYSA0 priority position. These bits cannot be changed dynamically.
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Integrated Programmable Interrupt Controller (IPIC) Table 8-18 defines the bit fields of SEPNR. Table 8-18. SEPNR Field Descriptions Bits Name 0, 1, 2, 3 IRQn Each bit corresponds to an external interrupt source. When an external interrupt is received, the interrupt controller sets the corresponding SEPNR bit. When a pending interrupt is handled, the user must clear the corresponding SEPNR bit.
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Integrated Programmable Interrupt Controller (IPIC) 8.5.12 System Mixed Interrupt Group B Priority Register (SMPRR_B) SMPRR_B, shown in Figure 8-15, defines the priority among the sources listed in Table 8-20. Offset 0x34 0 Access: Read/write 2 3 5 6 8 9 11 12 15 16 18 19 21 22 24 25 27 28 31 R MIXB0P MIXB1P MIXB2P MIXB3P 0 0 0 — MIXB4P MIXB5P MIXB6P MIXB7P 1 1 1 1 — W Reset 0 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 1 1 0 1 1 0 0 0 0 Figure 8-15.
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Integrated Programmable Interrupt Controller (IPIC) Offset 0x38 Access: Read/write 0 R 1 2 3 4 15 IRQ01 IRQ1 IRQ2 IRQ3 — W Reset All Zeros 16 17 31 R SIRQ0 — W Reset All zeros 1 This bit is valid only if the IRQ0 signal is configured as an external maskable interrupt (SEMSR[SIRQ0] = 0) Figure 8-16. System External Interrupt Mask Register (SEMSR) Table 8-21 defines the bit fields of SEMSR. Table 8-21.
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Integrated Programmable Interrupt Controller (IPIC) Offset 0x3C Access: Read/write 0 1 2 3 4 7 8 9 10 11 12 15 R MIXB0T MIXB1T — MIXA0T MIXA1T — W Reset All zeros 16 17 18 19 EDI0 EDI1 EDI2 EDI3 20 31 R — W Reset All zeros Figure 8-17. System External Interrupt Control Register (SECNR) Table 8-22 defines the bit fields of SECNR. Table 8-22. SECNR Field Descriptions Bits Name Description 0–1 MIXB0T MIXB0 priority position IPIC output interrupt type.
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Integrated Programmable Interrupt Controller (IPIC) 8.5.15 System Error Status Register (SERSR) The bits in the SERSR, shown in Figure 8-18, correspond to the external and internal non-maskable error source machine check (mcp) conditions listed in Table 8-23. When an error interrupt signal is received, the interrupt controller sets the corresponding SERSR bit. Offset 0x40 Access: Read/write 0 31 R INTn (Implemented bits are listed in Table 8-23) W Reset All zeros Figure 8-18.
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Integrated Programmable Interrupt Controller (IPIC) Offset 0x44 Access: Read/write 0 31 R INTn (Implemented bits are listed in Table 8-23.) W Reset Implemented bits reset to ones; unimplemented (reserved) bits reset to zeros. Figure 8-19. System Error Mask Register (SERMR) Table 8-25 defines the bit fields of SERMR. Table 8-25. SERMR Field Descriptions Bits Name 0–31 INTn Each implemented SERMR bit, listed in Table 8-23, corresponds to an external and an internal MCP source.
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Integrated Programmable Interrupt Controller (IPIC) pin. The active high signals assert an interrupt request upon either a low-to-high change or assertion (high state) on the pin. See Section 8.5.14, “System External Interrupt Control Register (SECNR),” on page 8-23 for more details. NOTE Note that the IRQn signals are overbarred although the SEPCR could be programmed to accept active high signals. The overbar should be ignored in this case.
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Integrated Programmable Interrupt Controller (IPIC) Table 8-28 defines the bit fields of SIFCR_H. Table 8-28. SIFCR_H Field Descriptions Bits Name Description 0–31 INTn Each implemented bit, listed in Table 8-7, corresponds to an internal interrupt source. The user forces an interrupt by setting the corresponding SIFCRx bit. SIFCRn bit positions are not changed according to their relative priority. Writes to unimplemented (reserved) bits are ignored; read = 0 SIFCR_L is shown in Figure 8-23.
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Integrated Programmable Interrupt Controller (IPIC) 8.5.20 System External Interrupt Force Register (SEFCR) Each implemented bit in SEFCR, shown in Figure 8-24, corresponds to an external interrupt source. When a bit is set, the interrupt controller generates the corresponding external interrupt (sets the corresponding SEPNR bit). SEFCR can be read by the user at any time.
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Integrated Programmable Interrupt Controller (IPIC) Table 8-31 defines the bit fields of SERFR. Table 8-31. SERFR Field Descriptions Bits Name 0–31 Description INTn Each implemented bit, listed in Table 8-23, corresponds to an external MCP source. The user forces an MCP by setting the SERFR bit. SERFR bit positions are not affected by their relative priority. Attempts to write to unimplemented (reserved) bits are ignored; read = 0 8.5.
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Integrated Programmable Interrupt Controller (IPIC) Note that in core disabled mode, the user should use SIVCR only read an updated interrupt vector (SMVCR should not be used). Offset 0x64 Access: Read only 0 5 R 6 24 25 MVECx 31 MVEC — W Reset All zeros Figure 8-27. System Management Interrupt Vector Register (SMVCR) Table 8-33 defines the bit fields of SMVCR. Table 8-33.
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Integrated Programmable Interrupt Controller (IPIC) 8.6.2 Interrupt Configuration mcp System Bus Arbiter (SBA) mcp WDT ext mcp MCP Interrupts (Internal and External) Figure 8-28 shows the interrupt configuration. mcp IRQ[0] MPC8308 Interrupt Controller IRQ[0], IRQ[1] IRQ[2], IRQ[3] e300 Core ext int 4 4 int cint smi PIT DMA GTM1 2 2 System Interrupts (Internal and External) RTC 4 DDR MEMC LB MEMC PCI Express eTSEC 1 eTSEC 2 eSDHC DUART I2C SPI System Bus Arbiter (SBA) GPIO MSIR USB 2.
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Integrated Programmable Interrupt Controller (IPIC) All interrupt sources are prioritized and bits are set in the system interrupt pending register (SIPNR, SEPNR) as interrupts occur regardless of whether they are masked in the IPIC. The prioritization of the interrupt sources is flexible within the following groups: • The relative priority of the eTSEC1 Tx, eTSEC1 Rx, eTSEC1 Err, eTSEC2 Tx, eTSEC2 Rx, eTSEC2 Err, and USB DR internal interrupt signals can be modified.
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Integrated Programmable Interrupt Controller (IPIC) • 8.6.5 Spread. In the spread scheme, priorities are spread over the table so other sources can have lower interrupt latencies. This scheme is also programmed but cannot be changed dynamically. Highest Priority Interrupt In addition to the group relative priority option, SICFR[HPI] can be used to specify one interrupt source as having the highest priority.
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Integrated Programmable Interrupt Controller (IPIC) Table 8-34.
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Integrated Programmable Interrupt Controller (IPIC) Table 8-34.
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Integrated Programmable Interrupt Controller (IPIC) Table 8-34.
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Integrated Programmable Interrupt Controller (IPIC) Table 8-34. Interrupt Source Priority Levels (continued) 8.6.7 Priority Interrupt Source Description 124 DMAC Err 125 SYSC7 (Spread) 126 SYSD7 (Spread) 127 Reserved 128 Reserved Masking Interrupt Sources By programming the system interrupt mask registers, SIMSRx and SEMSR, the user can mask interrupt requests to the core. Each SIMSRx and SEMSR bit corresponds to an interrupt source.
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Integrated Programmable Interrupt Controller (IPIC) Figure 8-29 shows an example of how the masking occurs using a DDR block. DDR EVENT SIPNR Event Bit XX Input (or XX Event Bits) Request to the core (Other Unmasked Requests) DDR MASK SIMSR Mask Bit Mask Bit Figure 8-29. DDR Interrupt Request Masking 8.6.8 Interrupt Vector Generation and Calculation Pending unmasked interrupts are presented to the core in order of priority according to Table 8-34.
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Integrated Programmable Interrupt Controller (IPIC) 8.7 Message Shared Interrupts The massage shared interrupt (MSI) registers enable the PCI Express end points to generate interrupt requests to the local e300 CPU. Each end point can generate an interrupt and set a unique bit in one of the eight MSIR registers. Clearing the MSIR register happens immediately after the read of its content, and by then a new set operation can begin. MSIRn is considered active if it contains at least one bit set.
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Integrated Programmable Interrupt Controller (IPIC) Figure 8-30 shows the message shared interrupt registers. Offset 0xC0 0xC4 0xC8 0xCC 0 0xD0 0xD4 0xD8 0xDC 1 2 3 4 Access: Special 5 6 7 8 9 10 11 12 13 14 15 R SH31 SH30 SH29 SH28 SH27 SH26 SH25 SH24 SH23 SH22 SH21 SH20 SH19 SH18 SH17 SH16 W Reset All zeros 16 17 18 19 20 21 R SH15 SH14 SH13 SH12 SH11 SH10 22 23 24 25 26 27 28 29 30 31 SH9 SH8 SH7 SH6 SH5 SH4 SH3 SH2 SH1 SH0 W Reset All zeros Figure 8-30.
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Integrated Programmable Interrupt Controller (IPIC) Table 8-37. MSIMR Field Descriptions (continued) Bits Name 26 M5 Mask 5. Set to 1 masks interrupt generation for message shared interrupt register 5 27 M4 Mask 4. Set to 1 masks interrupt generation for message shared interrupt register 4 28 M3 Mask 3. Set to 1 masks interrupt generation for message shared interrupt register 3 29 M2 Mask 2. Set to 1 masks interrupt generation for message shared interrupt register 2 30 M1 Mask 1.
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Integrated Programmable Interrupt Controller (IPIC) Figure 8-33 shows the message shared interrupt index register. Offset 0xF8 0 Access: Write only 2 3 7 8 31 R W SRS — IBS Reset All zeros Figure 8-33. Message Shared Interrupt Index Register (MSIIR) Table 8-39 describes the bits of the MSIIRs. Table 8-39. MSIIR Field Descriptions Bits Name Description 0–2 SRS Shared interrupt register select. Select the message shared interrupt register.
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Integrated Programmable Interrupt Controller (IPIC) MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev.
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Chapter 9 DDR Memory Controller 9.1 Introduction The fully programmable DDR SDRAM controller supports most JEDEC standard 8, 16, and 32 DDR2 memories available. In addition, unbuffered and registered DIMMs are supported. However, mixing different memory types or unbuffered and registered DIMMs in the same system is not supported. Built-in error checking and correction (ECC) ensures very low bit-error rates for reliable high-frequency operation.
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DDR Memory Controller Figure 9-1 is a high-level block diagram of the DDR memory controller with its associated interfaces. Section 9.5, “Functional Description,” contains detailed figures of the controller.
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DDR Memory Controller • • • • • • • • • 9.2.1 — Unbuffered and registered DIMMs Chip select interleaving support Support for data mask signals and read-modify-write for sub-double-word writes. Note that a read-modify-write sequence is only necessary when ECC is enabled.
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DDR Memory Controller Table 9-1 shows how DDR memory controller external signals are grouped. The device hardware specification has a pinout diagram showing pin numbers. It also lists all electrical and mechanical specifications. Table 9-1.
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DDR Memory Controller Table 9-2 shows the memory address signal mappings. Table 9-2.
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DDR Memory Controller 9.3.2 Detailed Signal Descriptions The following sections describe the DDR SDRAM controller input and output signals, the meaning of their different states, and relative timing information for assertion and negation. 9.3.2.1 Memory Interface Signals Table 9-3 describes the DDR controller memory interface signals. Table 9-3. Memory Interface Signals—Detailed Signal Descriptions Signal MDQ[0:31] I/O Description I/O Data bus.
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DDR Memory Controller Table 9-3. Memory Interface Signals—Detailed Signal Descriptions (continued) Signal MECC[0:7] I/O Description I/O Error checking and correcting codes. Input and output signals for the DDR controller’s bidirectional ECC bus. MECC[0:5] function in both normal and debug modes. O ECC signals represent the state of ECC driven by the DDR controller on writes. See Section 9.5.11, “Error Checking and Correcting (ECC),” for more details.
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DDR Memory Controller Table 9-3. Memory Interface Signals—Detailed Signal Descriptions (continued) Signal I/O Description MRAS O Row address strobe. Active-low SDRAM address multiplexing signal. Asserted for activate commands. In addition; used for mode register set commands and refresh commands. State Asserted—Indicates that a valid SDRAM row address is on the address bus for read and Meaning write transactions.
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DDR Memory Controller 9.3.2.2 Clock Interface Signals Table 9-4 contains the detailed descriptions of the clock signals of the DDR controller. Table 9-4. Clock Signals—Detailed Signal Descriptions Signal I/O MCK[0:2], MCK[0:2] O Description DRAM clock output and its complement. See Section 9.5.4.1, “Clock Distribution.” State Asserted/Negated—The JEDEC DDR SDRAM specifications require true and complement Meaning clocks. A clock edge is seen by the SDRAM when the true and complement cross.
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DDR Memory Controller Table 9-5. DDR Memory Controller Memory Map (continued) Offset Register Reset Section/Page 0x110 DDR_SDRAM_CFG—DDR SDRAM control configuration R/W 0x0200_0000 9.4.1.7/9-19 0x114 DDR_SDRAM_CFG_2—DDR SDRAM control configuration 2 R/W 0x0000_0000 9.4.1.8/9-22 0x118 DDR_SDRAM_MODE—DDR SDRAM mode configuration R/W 0x0000_0000 9.4.1.9/9-23 0x11C DDR_SDRAM_MODE_2—DDR SDRAM mode configuration 2 R/W 0x0000_0000 9.4.1.
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DDR Memory Controller If chip select interleaving is enabled, all fields in the lower interleaved chip select are used, and the other chip selects’ bounds registers are unused. For example, if chip selects 0 and 1 are interleaved, all fields in CS0_BNDS are used, and all fields in CS1_BNDS are unused. CSn_BNDS are shown in Figure 9-2. Offset 0x000, 0x008 0 Access: Read/Write 7 R — W 8 15 16 SAn Reset 23 24 — 31 EAn All zeros Figure 9-2.
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DDR Memory Controller For example, if chip selects 0 and 1 are interleaved, all fields in CS0_CONFIG are used, but only the ODT_RD_CFG and ODT_WR_CFG fields in CS1_CONFIG are used. Offset 0x080, 0x084 0 R W Access: Read/Write 1 7 CS_n _EN — AP_n_EN Reset W 9 11 ODT_RD_CFG 12 — 13 15 ODT_WR_CFG All zeros 16 R 8 17 18 BA_BITS_CS_n 20 — 21 23 24 ROW_BITS_CS_n Reset 28 — 29 31 COL_BITS_CS_n All zeros Figure 9-3.
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DDR Memory Controller Table 9-7. CSn_CONFIG Field Descriptions (continued) Bits Name 18–20 — 21–23 Description Reserved ROW_BITS_CS_n Number of row bits for SDRAM on chip select n. See Table 9-38 for details. 000 12 row bits 001 13 row bits 010 14 row bits 011–111 Reserved 24–28 — 29–31 COL_BITS_CS_n 9.4.1.3 Reserved Number of column bits for SDRAM on chip select n.
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DDR Memory Controller 9.4.1.4 DDR SDRAM Timing Configuration 0 (TIMING_CFG_0) DDR SDRAM timing configuration register 0, shown in Figure 9-5, sets the number of clock cycles between various SDRAM control commands. Offset 0x104 0 R W 1 Access: Read/Write 2 3 4 5 RWT WRT RRT Reset 0 0 0 0 0 0 6 7 8 9 11 12 13 15 WWT — ACT_PD_EXIT — PRE_PD_EXIT 0 0 0 0 0 1 0 0 0 1 16 19 20 — 0 0 0 0 23 24 ODT_PD_EXIT 0 0 0 1 27 28 — 31 MRS_CYC 0 0 0 0 0 1 0 1 Figure 9-5.
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DDR Memory Controller Table 9-9. TIMING_CFG_0 Field Descriptions (continued) Bits 9–11 Name Description ACT_PD_EXIT Active powerdown exit timing (tXARD and tXARDS). Specifies how many clock cycles to wait after exiting active powerdown before issuing any command. 000 001 010 011 12 13–15 — 20–23 100 101 110 111 4 clocks 5 clocks 6 clocks 7 clocks Reserved, should be cleared. PRE_PD_EXIT Precharge powerdown exit timing (tXP).
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DDR Memory Controller 9.4.1.5 DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) DDR SDRAM timing configuration register 1, shown in Figure 9-6, sets the number of clock cycles between various SDRAM control commands. Offset 0x108 0 R W 1 Access: Read/Write 3 4 — PRETOACT 7 ACTTOPRE 8 9 11 12 — ACTTORW Reset 15 16 CASLAT 19 20 21 REFREC 23 24 25 27 28 29 31 — WRREC — ACTTOACT — WRTORD All zeros Figure 9-6.
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DDR Memory Controller Table 9-10. TIMING_CFG_1 Field Descriptions (continued) Bits Name Description 12–15 CASLAT MCAS latency from READ command. Number of clock cycles between registration of a READ command by the SDRAM and the availability of the first output data. If a READ command is registered at clock edge n and the latency is m clocks, data is available nominally coincident with clock edge n + m. This value must be programmed at initialization as described in Section 9.4.1.
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DDR Memory Controller 9.4.1.6 DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) DDR SDRAM timing configuration 2, shown in Figure 9-7, sets the clock delay to data for writes. Offset 0x10C 0 R W — Access: Read/Write 1 3 4 ADD_LAT 8 9 CPO 10 12 13 — WR_LAT 15 — Reset 16 18 19 21 22 23 25 26 RD_TO_PRE WR_DATA_DELAY — CKE_PLS 31 FOUR_ACT All zeros Figure 9-7. DDR SDRAM Timing Configuration 2 Register (TIMING_CFG_2) Table 9-11 describes the TIMING_CFG_2 fields. Table 9-11.
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DDR Memory Controller Table 9-11. TIMING_CFG_2 Field Descriptions (continued) Bits Name Description 13–15 — 16–18 RD_TO_PRE Reserved Read to precharge (tRTP). For DDR2, with a non-zero ADD_LAT value, takes a minimum of ADD_LAT + tRTP cycles between read and precharge. 000 001 010 011 Reserved 1 cycle 2 cycles 3 cycles 100 4 cycles 101–111 Reserved 19–21 WR_DATA_DELAY Write command to write data strobe timing adjustment. Controls the amount of delay applied to the data and data strobes for writes.
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DDR Memory Controller Table 9-12 describes the DDR_SDRAM_CFG fields. Table 9-12. DDR_SDRAM_CFG Field Descriptions Bits Name 0 MEM_EN 1 SREN 2 ECC_EN 3 RD_EN 4 — 5–7 SDRAM_TYPE 8–9 — 10 DYN_PWR 11–12 DBW 13 — 14 NCAP 15 — 16 2T_EN Description DDR SDRAM interface logic enable. 0 SDRAM interface logic is disabled. 1 SDRAM interface logic is enabled. Must not be set until all other memory configuration parameters have been appropriately configured by initialization code.
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DDR Memory Controller Table 9-12. DDR_SDRAM_CFG Field Descriptions (continued) Bits Name 17–23 BA_INTLV_CTL 24–26 — 27 PCHB8 28 HSE Description Bank (chip select) interleaving control. Set this field only if you wish to use bank interleaving. (All unlisted field values are reserved.) 0000000No external memory banks are interleaved 1000000External memory banks 0 and 1 are interleaved Reserved Precharge bit 8 enable. 0 MA[10] is used to indicate the auto-precharge and precharge all commands.
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DDR Memory Controller 9.4.1.8 DDR SDRAM Control Configuration 2 (DDR_SDRAM_CFG_2) The DDR SDRAM control configuration register 2, shown in Figure 9-9, provides more control configuration for the DDR controller. Offset 0x114 R W Access: Read/Write 0 1 FRC_SR — 2 3 4 5 6 8 DLL_RST_DIS — DQS_CFG Reset 9 — 10 11 15 ODT_CFG — All zeros 16 19 R 20 26 NUM_PR W — Reset 27 28 D_INIT 31 — All zeros Figure 9-9.
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DDR Memory Controller Table 9-13. DDR_SDRAM_CFG_2 Field Descriptions (continued) Bits Name Description 16–19 NUM_PR Number of posted refreshes. This determines how many posted refreshes, if any, can be issued at one time. Note that if posted refreshes are used, then this field, along with DDR_SDRAM_INTERVAL[REFINT], must be programmed such that the maximum tras specification cannot be violated.
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DDR Memory Controller Table 9-14 describes the DDR_SDRAM_MODE fields. Table 9-14. DDR_SDRAM_MODE Field Descriptions Bits Name Description 0–15 ESDMODE Extended SDRAM mode. Specifies the initial value loaded into the DDR SDRAM extended mode register. The range and meaning of legal values is specified by the DDR SDRAM manufacturer.
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DDR Memory Controller 9.4.1.11 DDR SDRAM Mode Control Register (DDR_SDRAM_MD_CNTL) The DDR SDRAM mode control register, shown in Figure 9-12, allows the user to carry out the following tasks: • Issue a mode register set command to a particular chip select • Issue an immediate refresh to a particular chip select • Issue an immediate precharge or precharge all command to a particular chip select • Force the CKE signals to a specific value Table 9-16 describes the fields of this register.
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DDR Memory Controller Table 9-16. DDR_SDRAM_MD_CNTL Field Descriptions (continued) Bits Name Description 5–7 MD_SEL Mode register select. MD_SEL specifies one of the following: • During a mode select command, selects the SDRAM mode register to be changed • During a precharge command, selects the SDRAM logical bank to be precharged. A precharge all command ignores this field. • During a refresh command, this field is ignored.
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DDR Memory Controller Table 9-17. Settings of DDR_SDRAM_MD_CNTL Fields (continued) Field Mode Register Set CS_SEL Refresh Clock Enable Signals Control Precharge Chooses chip select (CS) — MD_SEL Select mode register. See Table 9-16. — Selects logical bank — MD_VALUE Value written to mode register — Only bit five is significant. See Table 9-16. — CKE_CNTL 0 0 0 9.4.1.12 See Table 9-16.
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DDR Memory Controller 9.4.1.13 DDR SDRAM Data Initialization (DDR_DATA_INIT) The DDR SDRAM data initialization register, shown in Figure 9-14, provides the value that is used to initialize memory if DDR_SDRAM_CFG2[D_INIT] is set. Offset 0x128 Access: Read/Write 0 31 R INIT_VALUE W Reset All zeros Figure 9-14. DDR SDRAM Data Initialization Configuration Register (DDR_DATA_INIT) Table 9-19 describes the DDR_DATA_INIT fields. Table 9-19.
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DDR Memory Controller 9.4.1.15 DDR Initialization Address (DDR_INIT_ADDR) The DDR SDRAM initialization address register, shown in Figure 9-16, provides the address that is used for the automatic CAS to preamble calibration after POR. Offset 0x148 Access: Read/Write 0 31 R INIT_ADDR W Reset All zeros Figure 9-16. DDR Initialization Address Configuration Register (DDR_INIT_ADDR) Table 9-21 describes the DDR_INIT_ADDR fields. Table 9-21.
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DDR Memory Controller 9.4.1.17 DDR IP Block Revision 2 (DDR_IP_REV2) The DDR IP block revision 2 register, shown in Figure 9-18, provides read-only fields with the IP block integration and configuration options. Offset 0xBFC Access: Read Only 0 7 R 8 — W Reset 0 0 0 15 16 IP_INT 0 0 0 0 0 n 23 24 — 31 IP_CFG n n n n n n n 0 0 0 0 0 0 0 0 n n n n n n n n Figure 9-18. DDR IP Block Revision 2 (DDR_IP_REV2) Table 9-23 describes the DDR_IP_REV2 fields. Table 9-23.
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DDR Memory Controller 9.4.1.19 Memory Data Path Error Injection Mask Low (DATA_ERR_INJECT_LO) The memory data path error injection mask low register is shown in Figure 9-20. Offset 0xE04 Access: Read/Write 0 31 R EIML W Reset All zeros Figure 9-20. Memory Data Path Error Injection Mask Low Register (DATA_ERR_INJECT_LO) Table 9-25 describes the DATA_ERR_INJECT_LO fields. Table 9-25. DATA_ERR_INJECT_LO Field Descriptions Bits Name Description 0–31 EIML Error injection mask low data path.
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DDR Memory Controller 9.4.1.21 Memory Data Path Read Capture High (CAPTURE_DATA_HI) The memory data path read capture high register, shown in Figure 9-22, stores the high word of the read data path during error capture. Offset 0xE20 Access: Read/Write 0 31 R ECHD W Reset All zeros Figure 9-22. Memory Data Path Read Capture High Register (CAPTURE_DATA_HI) Table 9-27 describes the CAPTURE_DATA_HI fields. Table 9-27.
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DDR Memory Controller 9.4.1.23 Memory Data Path Read Capture ECC (CAPTURE_ECC) The memory data path read capture ECC register, shown in Figure 9-24, stores the ECC syndrome bits that were on the data bus when an error was detected. Offset 0xE28 Access: Read/Write 0 31 R ECE W Reset All zeros Figure 9-24. Memory Data Path Read Capture ECC Register (CAPTURE_ECC) Table 9-29 describes the CAPTURE_ECC fields. Table 9-29. CAPTURE_ECC Field Descriptions Bits Name 0–31 ECE 9.4.1.
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DDR Memory Controller Table 9-30. ERR_DETECT Field Descriptions (continued) Bits Name 24 ACE 25–27 — 28 MBE Multiple-bit error. This bit is cleared by software writing a 1. 0 A multiple-bit error has not been detected. 1 A multiple-bit error has been detected. 29 SBE Single-bit ECC error. This bit is cleared by software writing a 1. 0 The number of single-bit ECC errors detected has not crossed the threshold set in ERR_SBE[SBET].
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DDR Memory Controller Table 9-31. ERR_DISABLE Field Descriptions (continued) Bits Name 30 — 31 Description Reserved MSED Memory select error disable 0 Memory select errors are enabled. 1 Memory select errors are disabled. 9.4.1.26 Memory Error Interrupt Enable (ERR_INT_EN) The memory error interrupt enable register, shown in Figure 9-27, enables ECC interrupts or memory select error interrupts.
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DDR Memory Controller 9.4.1.27 Memory Error Attributes Capture (CAPTURE_ATTRIBUTES) The memory error attributes capture register, shown in Figure 9-28, sets attributes for errors including type, size, source, and others. Offset 0xE4C 0 R W Access: Read/Write 1 — 3 BNUM 4 5 — 7 TSIZ 8 10 11 — Reset 15 16 17 18 19 20 TSRC — TTYP 30 — 31 VLD All zeros Figure 9-28. Memory Error Attributes Capture Register (CAPTURE_ATTRIBUTES) Table 9-33 describes the CAPTURE_ATTRIBUTES fields.
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DDR Memory Controller 9.4.1.28 Memory Error Address Capture (CAPTURE_ADDRESS) The memory error address capture register, shown in Figure 9-29, holds the 32 lsbs of a transaction when a DDR ECC error is detected. Offset 0xE50 Access: Read/Write 0 31 R CADDR W Reset All zeros Figure 9-29. Memory Error Address Capture Register (CAPTURE_ADDRESS) Table 9-34 describes the CAPTURE_ADDRESS fields. Table 9-34. CAPTURE_ADDRESS Field Descriptions Bits 0–31 Name Description CADDR Captured address.
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DDR Memory Controller 9.5 Functional Description The DDR SDRAM controller controls processor and I/O interactions with system memory. It provides support for JEDEC-compliant DDR2 SDRAM. The memory system allows a wide range of memory devices to be mapped to any arbitrary chip select, and support is provided for registered DIMMs and unbuffered DIMMs. However, registered DIMMs cannot be mixed with unbuffered DIMMs. Figure 9-1 is a high-level block diagram of the DDR memory controller.
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DDR Memory Controller Figure 9-31 shows an example DDR SDRAM configuration with four logical banks. Data Bus Data-Out Registers Data-In Registers SDRAM MUX, MASK, Read Data Latch ADDR COMMAND: MCS, MRAS, MCAS, MWE Control DQM Logical Bank 0 Logical Bank 1 Logical Bank 2 Logical Bank 3 BA1,BA0 CKE, MCK, MCK Figure 9-31. Typical Dual Data Rate SDRAM Internal Organization Figure 9-32 shows some typical signal connections.
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DDR Memory Controller and board routing loads can assist the system designer in deciding signal buffering requirements. The DDR memory controller drives 14 address pins, but in this example the DDR SDRAM devices use only 12 bits. MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev.
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DDR Memory Controller MDQS[0:3] MDQS[8] MDQ[0:31] ECC[0:7] Memory Data Bus and Strobes MA[13:0] MBA[2:0] MRAS To all SDRAM Devices in Common MCAS MWE MCKE MCK[0:2] MCK[0:2] MCS[0:1] DDR Controller 0 1 2 3 MDM[0:3], MDM[8] 8M8 SDRAM 2Mx8 SDRAM A[11:0] 2Mx8 SDRAM BA[1:0] A[0-11] RAS 2Mx8MDQS SDRAM BA[0-1] A(11-0) CAS RAS BA(1-0) A(11-0) DQ[7:0] WE CAS RAS BA(1-0) CKE CAS RAS DQ[0-7] CK CKE CAS DQ(7-0) CS CLK CKE DQ(7-0) DM CS CLK CKE DM CS CLK DM CS DM 8M8 SDRAM 2Mx8 SDRAM A[11:0] 2Mx8 SDRAM BA[1:0
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DDR Memory Controller For information on how the DDR2 memory controller handles errors, see Section 9.5.12, “Error Management.” 9.5.1 DDR SDRAM Interface Operation The DDR memory controller supports many different DDR SDRAM configurations. SDRAMs with different sizes can be used in the same system. Fourteen multiplexed address signals and three logical bank select signals support device densities from 64 Mbits to 2 Gbits. Two chip select (CS) signals support two banks of DIMM of memory.
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DDR Memory Controller Table 9-37.
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DDR Memory Controller Table 9-38. DDR2 Address Multiplexing for 32-Bit Data Bus with Interleaving and Partial Array Self Refresh Disabled (continued) Row ¥ Col msb 0 Address from Core Master 1 2 3 4 5 13  MRAS 10  2 MBA 6 lsb 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30–31 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 MCAS 9 13  MRAS 92 MBA 12 11 10 9 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 0 1 0 MCAS Table 9-39.
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DDR Memory Controller Table 9-40 illustrates examples of address decode when interleaving between two chip selects. Table 9-40.
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DDR Memory Controller • • • • Latches column address and transfers data from the selected sense amplifier to the output buffer as determined by the column address. During each succeeding clock edge, additional data is driven without additional read commands. The amount of data transferred is determined by the burst size which defaults to 4. Write Latches column address and transfers data from the data pins to the selected sense amplifier as determined by the column address.
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DDR Memory Controller Table 9-41. DDR SDRAM Command Table (continued) CKE CKE MCS MRAS MCAS MWE Prev.
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DDR Memory Controller Table 9-42. DDR SDRAM Interface Timing Intervals (continued) Timing Intervals PRETOACT Definition The number of clock cycles from a precharge command until an activate or a refresh command is allowed. This interval is listed in the AC specifications of the SDRAM as tRP. REFINT Refresh interval. Represents the number of memory bus clock cycles between refresh cycles. Depending on DDR_SDRAM_CFG_2[NUM_PR], some number of rows are refreshed in each SDRAM bank during each refresh cycle.
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DDR Memory Controller set to 1/2 DRAM cycle, an additive latency of 0 DRAM cycles is used, and the write latency is 1 DRAM cycle. 0 1 2 3 4 5 6 7 8 9 10 11 12 SDRAM Clock MCS ACTTORW MRAS MCAS MAn ROW COL MWE COL CASLAT MDQn D0 D1 D2 D3 D0 D1 D2 D3 MDQS Figure 9-34.
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DDR Memory Controller 0 1 2 3 4 5 6 7 8 9 10 11 12 SDRAM Clock MCS0 MCS1 ACTTORW MRAS MCAS MAn ROW ROW COL COL COL COL MWE MDQ[0:63] D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D MDQS MDM[0:7] 00 Figure 9-36. DDR SDRAM Single-Beat (Double Word) Write Timing—ACTTORW = 3 9.5.4.1 Clock Distribution The following list discusses recommendations for clock distribution. • If running with many devices, zero-delay PLL clock buffers, JEDEC-JESD82 standard, should be used.
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DDR Memory Controller 9.5.5 DDR SDRAM Mode-Set Command Timing The DDR memory controller transfers the mode register set commands to the SDRAM array, and it uses the setting of TIMING_CFG_0[MRS_CYC] for the Mode Register Set cycle time. Figure 9-38 shows the timing of the mode-set command. The first transfer corresponds to the ESDMODE code; the second corresponds to SDMODE. The Mode Register Set cycle time is set to 2 DRAM cycles.
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DDR Memory Controller Figure 9-39 shows the registered DDR SDRAM DIMM single-beat write timing. 0 1 2 3 4 5 6 7 8 9 10 11 12 SDRAM Clock MCS ACTTORW MRAS MCAS MAn ROW COL COL MWE MDQn D0 D1 D2 D3 D0 D1 D2 D3 MDQS MDM[0:3] 00 Figure 9-39. Registered DDR SDRAM DIMM Burst Write Timing 9.5.
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DDR Memory Controller Figure 9-40 shows the use of the WR_DATA_DELAY parameter. 0 1 2 3 4 5 6 7 8 9 10 11 12 SDRAM Clock MCS ACTTORW MRAS MCAS MAn ROW COL COL MWE MDQn D0 D1 D2 D3 D0 D1 D2 D3 MDQS 1/4 Delay MDMn 00 MDQn D0 D1 D2 D3 D0 D1 D2 D3 1/2 Delay MDQS MDMn 00 Figure 9-40. Write Timing Adjustments Example for Write Latency = 1 9.5.8 DDR SDRAM Refresh The DDR memory controller supports auto-refresh and self-refresh.
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DDR Memory Controller The auto-refresh commands are staggered across the two possible banks to reduce the system’s instantaneous power requirements. Three sets of auto refresh commands are issued on consecutive cycles when the memory is populated with one DIMM. The initial PRECHARGE-ALL commands are also staggered in three groups for convenience. It is important to note that when entering self-refresh mode, only one refresh command is issued simultaneously to all physical banks.
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DDR Memory Controller Table 9-43 summarizes the refresh types available in each power-saving mode. Table 9-43. DDR SDRAM Power-Saving Modes Refresh Configuration Power Saving Mode Refresh Type SREN Sleep Self 1 None — Note that in the absence of refresh support, system software must preserve DDR SDRAM data (such as by copying the data to disk) before entering the power-saving mode.
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DDR Memory Controller 9.5.8.2.1 Self-Refresh in Sleep Mode The entry and exit timing for self-refreshing SDRAMs is shown in Figure 9-43 and Figure 9-44. 0 1 2 3 4 5 6 7 8 9 10 11 12 204 205 206 SDRAM Clock MCKE MCS MRAS MCAS MAn MWE (High Impedance) MDQn MDQS Figure 9-43. DDR SDRAM Self-Refresh Entry Timing 0 1 2 3 4 5 6 7 202 203 SDRAM Clock MCKE MCS MRAS MCAS MAn MWE MDQn MDQS (High Impedance) 200 Cycles Figure 9-44. DDR SDRAM Self-Refresh Exit Timing 9.5.
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DDR Memory Controller doubleword, a full read-modify-write is performed for a write to SDRAM. If ECC is disabled or both the access is doubleword aligned with a size that is a multiple of a doubleword, the data masks (MDM[0:4] for 32-bit bus) can be used to prevent the writing of unwanted data to SDRAM. The DDR memory controller also uses data masks to prevent all unintended full double words from writing to SDRAM.
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DDR Memory Controller in systems which use many different channels. Page mode is disabled by clearing DDR_SDRAM_INTERVAL[BSTOPRE] or setting CSn_CONFIG[AP_nEN]. 9.5.11 Error Checking and Correcting (ECC) The DDR memory controller supports error checking and correcting (ECC) for the data path between the core master and system memory. The memory detects all double-bit errors, detects all multi-bit errors within a nibble, and corrects all single-bit errors.
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DDR Memory Controller Table 9-45.
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DDR Memory Controller 9.5.12 Error Management The DDR memory controller detects four different kinds of errors: training, single-bit, multi-bit, and memory select errors. The following discussion assumes all the relevant error detection, correction, and reporting functions are enabled as described in Section 9.4.1.26, “Memory Error Interrupt Enable (ERR_INT_EN),” Section 9.4.1.25, “Memory Error Dis able (ERR_DISABLE),” and Section 9.4.1.24, “Memory Error Detect (ERR_DETECT).
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DDR Memory Controller At system reset, initialization software (boot code) must set up the programmable parameters in the memory interface configuration registers. See Section 9.4.1, “Register Descriptions,” for more detailed descriptions of the configuration registers. These parameters are shown in Table 9-48. Table 9-48. Memory Interface Configuration Register Initialization Parameters Name CSn_BNDS CSn_CONFIG Description Parameter Section/page SAn EAn 9.4.1.
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DDR Memory Controller 9.6.1 DDR SDRAM Initialization Sequence After configuration of all parameters is complete, system software must set DDR_SDRAM_CFG[MEM_EN] to enable the memory interface. Note that 200 s must elapse after DRAM clocks are stable (DDR_SDRAM_CLK_CNTL[CLK_ADJUST] is set and any chip select is enabled) before MEM_EN can be set, so a delay loop in the initialization code may be necessary if software is enabling the memory controller.
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Chapter 10 Enhanced Local Bus Controller This chapter describes the enhanced local bus controller (eLBC) block. It describes the external signals and the memory-mapped registers as well as a functional description of the general-purpose chip-select machine (GPCM), NAND Flash control machine (FCM), and user-programmable machines (UPMs) of the eLBC. Finally, it includes an initialization and applications information section with many specific examples of its use. 10.
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Enhanced Local Bus Controller 10.1.1 Overview The main component of the eLBC is its memory controller, which provides a seamless interface to many types of memory devices and peripherals. The memory controller is responsible for controlling four memory banks shared by a GPCM, an FCM, and up to three UPMs. As such, it supports a minimal glue logic interface to SRAM, EPROM, NOR Flash EEPROM, NAND Flash EEPROM, burstable RAM, regular DRAM devices, extended data output DRAM devices, and other peripherals.
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Enhanced Local Bus Controller • • • — Programmable command and data transfer sequences of up to eight steps supported — Generic command and address registers support proprietary flash interfaces — Block write locking to ensure system security and integrity Three user-programmable machines (UPMs) — Programmable-array-based machine controls external signal timing with a granularity of up to one quarter of an external bus clock period — User-specified control-signal patterns run when an internal master requ
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Enhanced Local Bus Controller 10.1.3.2 Source ID Debug Mode The eLBC provides the ID of a transaction source on external device pins. When those pins are selected, the 5-bit internal ID of the current transaction source appears on LSRCID[0:4] whenever valid address or data is available on the eLBC external pins. When LDVAL and LCS is asserted, valid address and data is captured from the LA and LD bus respectively.
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Enhanced Local Bus Controller Table 10-1. Signal Properties—Summary (continued) Name Alternate Function(s) Mode No.
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Enhanced Local Bus Controller Table 10-2. Enhanced Local Bus Controller Detailed Signal Descriptions (continued) Signal I/O LOE/LGPL2/ LFRE O LGPL3/ LFWP O LGTA/LGPL4/ LFRB/ LUPWAIT LGPL5 Description GPCM output enable/General-purpose line 2/FCM read enable. State Asserted/Negated—Controls the output buffer of memory when accessing Meaning memory/devices in GPCM mode. In UPM mode, LGPL2 is one of six general purpose signals; it is driven with a value programmed into the UPM array.
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Enhanced Local Bus Controller Table 10-2. Enhanced Local Bus Controller Detailed Signal Descriptions (continued) Signal I/O LDVAL O Description Local bus data valid (eLBC debug mode only) State Asserted/Negated—For a read, LDVAL asserts for one bus cycle in the cycle immediately Meaning preceding the sampling of read data on LD. For a write, LDVAL asserts for one bus cycle during the final cycle for which the current write data on LD is valid. During burst transfers, LDVAL asserts for each data beat.
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Enhanced Local Bus Controller Table 10-3. Enhanced Local Bus Controller Registers (continued) Enhanced Local Bus Controller—Block Base Address 0x0_5000 Offset Register Access Reset Section/Page 0x070 MAMR—UPMA mode register R/W 0x0000_0000 10.3.1.4/10-19 0x074 MBMR—UPMB mode register R/W 0x0000_0000 10.3.1.4/10-19 0x078 MCMR—UPMC mode register R/W 0x0000_0000 10.3.1.4/10-19 — — — 0x07C– 0x080 Reserved 0x084 MRTPR—Memory refresh timer prescaler register R/W 0x0000_0000 10.3.1.
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Enhanced Local Bus Controller Table 10-3. Enhanced Local Bus Controller Registers (continued) Enhanced Local Bus Controller—Block Base Address 0x0_5000 Offset Register Access Reset Section/Page 0x100 FECC0—Flash ECC block 0 register R 0x0000_0000 10.3.1.23/10-38 0x104 FECC1—Flash ECC block 1 register R 0x0000_0000 10.3.1.23/10-38 0x108 FECC2—Flash ECC block 2 register R 0x0000_0000 10.3.1.23/10-38 0x10C FECC3—Flash ECC block 3 register R 0x0000_0000 10.3.1.23/10-38 10.3.
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Enhanced Local Bus Controller Table 10-4 describes BRn fields. Table 10-4. BRn Field Descriptions Bits Name Description 0–16 BA Base address. The upper 17 bits of each base register are compared to the address on the address bus to determine if the bus master is accessing a memory bank controlled by the memory controller. Used with the address mask bits ORn[AM]. 17–18 — Reserved 19–20 PS Port size. Specifies the port size of this memory region.
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Enhanced Local Bus Controller The ORn registers are interpreted differently depending on which of the three machine types is selected for that bank. Because bank 0 can be used to boot, the reset value of OR0 may be different depending on power-on configuration options. Table 10-5 shows the reset values for OR0. Table 10-5. Reset value of OR0 Register 10.3.1.2.
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Enhanced Local Bus Controller Table 10-6. Memory Bank Sizes in Relation to Address Mask (continued) 10.3.1.2.2 AM Memory Bank Size 1111_1111_1111_1111_0 64 Kbytes 1111_1111_1111_1111_1 32 Kbytes Option Registers (ORn)—GPCM Mode Figure 10-3 shows the bit fields for ORn when the corresponding BRn[MSEL] selects the GPCM machine.
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Enhanced Local Bus Controller Table 10-7. ORn—GPCM Field Descriptions (continued) Bits 20 21–22 Name Description CSNT Chip select negation time. Determines when LCSn and LWE are negated during an external memory write access handled by the GPCM, provided that ACS  00 (when ACS = 00, only LWE is affected by the setting of CSNT). This helps meet address/data hold times for slow memories and peripherals. 0 LCSn and LWE are negated normally.
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Enhanced Local Bus Controller Table 10-7. ORn—GPCM Field Descriptions (continued) Bits Name 29 TRLX 30 EHTR Extended hold time on read accesses. Indicates with TRLX how many cycles are inserted between a read access from the current bank and the next access. 31 Description Timing relaxed. Modifies the settings of timing parameters for slow memories or peripherals. 0 Normal timing is generated by the GPCM.
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Enhanced Local Bus Controller Table 10-8 describes ORn fields for FCM mode. Table 10-8. ORn—FCM Field Descriptions Bits Name Description 0–16 AM FCM address mask. Masks corresponding BRn bits. Masking address bits independently allows external devices of different size address ranges to be used. Address mask bits can be set or cleared in any order in the field, allowing a resource to reside in more than one area of the address map. 0 Corresponding address bits are masked.
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Enhanced Local Bus Controller Table 10-8. ORn—FCM Field Descriptions (continued) Bits Name 24 CHT Description Command hold time. Determines the LFWE0 negation prior to the command, address, or data change when the external memory access is handled by the FCM. TRLX CHT Meaning 0 0 The write-enable is negated 0.5 clock cycles before any command, address, or data change. 0 1 The write-enable is negated 1 clock cycle before any command, address, or data change. 1 0 The write-enable is negated 1.
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Enhanced Local Bus Controller Table 10-8. ORn—FCM Field Descriptions (continued) Bits Name Description 30 EHTR Extended hold time on read accesses. Indicates with TRLX how many cycles are inserted between a read access from the current bank and the next access. 31 — 10.3.1.2.4 TRLX EHTR Meaning 0 0 1 idle clock cycle is inserted. 0 1 2 idle clock cycles are inserted. 1 0 4 idle clock cycles are inserted. 1 1 8 idle clock cycles are inserted.
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Enhanced Local Bus Controller Table 10-9. ORn—UPM Field Descriptions (continued) Bits 19 Name Description BCTLD Buffer control disable. Disables assertion of LBCTL during access to the current memory bank. 0 LBCTL is asserted upon access to the current memory bank. 1 LBCTL is not asserted upon access to the current memory bank. 20–22 — Reserved 23 BI Burst inhibit. Indicates if this memory bank supports burst accesses. 0 The bank supports burst accesses. 1 The bank does not support burst accesses.
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Enhanced Local Bus Controller 10.3.1.4 UPM Mode Registers (MxMR) The UPM machine mode registers (MAMR, MBMR and MCMR), shown in Figure 10-7, contain the configuration for the three UPMs. Offset MAMR: 0x0_5070 MBMR: 0x0_5074 MCMR: 0x0_5078 R W 0 1 — RFEN Access: Read/Write 2 3 OP 4 5 UWPL 7 — Reset W 9 10 DS 12 G0CL 13 GPL4 14 15 RLF All zeros 16 R 8 17 18 21 RLF WLF 22 25 26 TLF Reset 31 MAD All zeros Figure 10-7.
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Enhanced Local Bus Controller Table 10-11. MxMR Field Descriptions (continued) Bits Name Description 8–9 DS Disable timer period. Guarantees a minimum time between accesses to the same memory bank controlled by UPMn. The disable timer is turned on by the TODT bit in the RAM array word, and when expired, the UPMn allows the machine access to handle a memory pattern to the same bank. Accesses to a different bank by the same UPMn is also allowed.
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Enhanced Local Bus Controller Table 10-11. MxMR Field Descriptions (continued) Bits Name Description 22–25 TLF Refresh loop field. Determines the number of times a loop defined in the UPMn will be executed for a refresh service pattern. 0000 16 0001 1 0010 2 0011 3 ... 1110 14 1111 15 26–31 MAD Machine address. RAM address pointer for the command executed. This field is incremented by 1, each time the UPM is accessed and the OP field is set to WRITE or READ. Address range is 64 words per UPMn. 10.
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Enhanced Local Bus Controller Offset 0x0_5088 Access: Read/Write 0 31 R D W Reset All zeros Figure 10-9. UPM Data Register in UPM Mode (MDR) Offset 0x0_5088 Access: Read/Write 0 7 R 8 AS3 W 15 16 AS2 Reset 23 24 AS1 31 AS0 All zeros Figure 10-10. FCM Data Register in FCM Mode (MDR) Table 10-13 describes MDR[D]. Table 10-13.
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Enhanced Local Bus Controller Mode Register (FMR).” Writing LSOR has the same effect as setting a special controller mode and performing a dummy access to a bank associated with the controller in question, but use of LSOR avoids changing settings for the address space occupied by the bank. More details of special operation sequences appear in Section 10.4.4.2.1, “UPM Programming Example (Two Sequential Writes to the RAM Array).
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Enhanced Local Bus Controller Table 10-15 describes LURT fields. Table 10-15. LURT Field Descriptions Bits Name Description 0–7 LURT UPM refresh timer period. Determines, along with the timer prescaler (MRTPR), the timer period according to the following equation: LURT TimerPeriod = ---------------------------------------------Fsystemclock  ----------------------------------------  MRTPR  PTP  Example: For a 266-MHz system clock and a required service rate of 15.
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Enhanced Local Bus Controller Table 10-16 describes LTESR fields. Table 10-16. LTESR Field Descriptions Bits Name Description 0 BM Bus monitor time-out 0 No local bus monitor time-out occurred. 1 Local bus monitor time-out occurred. No data beat was acknowledged on the bus within LBCR[BMT] x LBCR[BMTPS] bus clock cycles from the start of a transaction. 1 FCT FCM command time-out 0 No FCM command time-out occurred.
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Enhanced Local Bus Controller 10.3.1.10 Transfer Error Check Disable Register (LTEDR) The transfer error check disable register (LTEDR), shown in Figure 10-14, is used to disable error/event checking. Note that control of error/event checking is independent of control of reporting of errors/events (LTEIR) through the interrupt mechanism.
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Enhanced Local Bus Controller 10.3.1.11 Transfer Error Interrupt Enable Register (LTEIR) The transfer error interrupt enable register (LTEIR), shown in Figure 10-15, is used to send or block error/event reporting through the eLBC internal interrupt mechanism. Software should clear pending errors/events in LTESR before enabling interrupts. After an interrupt has occurred, clearing relevant LTESR error/event bits negates the interrupt.
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Enhanced Local Bus Controller Table 10-18. LTEIR Field Descriptions (continued) Bits Name 30 UCCI 31 CCI Description UPM Run pattern command completion Event interrupt enable. 0 UPM Run pattern command completion reporting is disabled. 1 UPM Run pattern command completion reporting is enabled. FCM command completion Event interrupt enable. 0 Command completion reporting is disabled. 1 Command completion reporting is enabled. 10.3.1.
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Enhanced Local Bus Controller 10.3.1.13 Transfer Error Address Register (LTEAR) The transfer error address register (LTEAR) captures the address of a transaction that caused an error/event. The transfer error address register (LTEAR) is shown in Figure 10-17. Offset 0x0_50C0 Access: Read/Write 0 31 R A W Reset All zeros Figure 10-17. Transfer Error Address Register (LTEAR) Table 10-20 describes LTEAR fields. Table 10-20.
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Enhanced Local Bus Controller 10.3.1.15 Local Bus Configuration Register (LBCR) The local bus configuration register (LBCR) is shown in Figure 10-19. Offset 0x0_50D0 0 R W Reset Access: Read/Write 1 7 LDIS 8 — 0 0 0 0 0 0 0 0 0 23 24 BMT W 10 11 15 BCTLC 16 R 9 — 0 0 0 0 27 28 1 0 31 — Reset 0 BMTPS All zeros Figure 10-19. Local Bus Configuration Register Table 10-22 describes LBCR fields. Table 10-22.
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Enhanced Local Bus Controller Table 10-22. LBCR Field Descriptions (continued) Bits Name Description 24–27 — 28–31 BMTPS Reserved Bus monitor timer prescale. Defines the multiplier, PS, to scale LBCR[BMT] for determining bus time-outs. 0000 PS = 8 0001 PS = 16 0010 PS = 32 0011 PS = 64 0100 PS = 128 0101 PS = 256 0110 PS = 512 0111 PS = 1024 1000 PS = 2048 1001 PS = 4096 1010 PS = 8192 1011 PS = 16,384 1100 PS = 32,768 1101 PS = 65,536 1110 PS = 131,072 1111 PS = 262,144 10.3.1.
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Enhanced Local Bus Controller Table 10-23 describes LCRR fields. Table 10-23. LCRR Field Descriptions Bits Name Description 0 PBYP 1–26 — Reserved Although bit 14 and 15 are reserved, they can be still programmed with the following to provide additional delay to LCLK: 00 4 01 1 10 2 11 3 27–31 CLKDIV System clock divider. Sets the frequency ratio between the system clock and the local bus clock. The system clock is equivalent to csb_clk or twice csb_clk (if RCWL[LBCM] is set).
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Enhanced Local Bus Controller Table 10-24 describes FMR fields. Table 10-24. FMR Field Descriptions Bits Name 0–15 — 16–19 BOOT 21–22 — 24–25 Reserved CWTO Command wait time-out. For FCM commands that wait on LFRB being sampled high (CW0, CW1, RBW and RSW), FCM pauses execution of the instruction sequence until either LFRB is sampled high, or a timer controlled by CTO expires, whichever occurs first.
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Enhanced Local Bus Controller Table 10-24. FMR Field Descriptions (continued) Bits Name Description 26–27 AL Address length. AL sets the number of address bytes issued during page address (PA) operations. However, the number of address bytes issued for column address (CA) operations is determined by the device page size (for ORn[PGS] = 0, 1 CA byte is issued; for ORn[PGS] = 1, 2 CA bytes are issued).
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Enhanced Local Bus Controller Table 10-25 describes FIR fields. Table 10-25. FIR Field Descriptions Bits Name Description 0–3 OP0 4–7 OP1 8–11 OP2 12–15 OP3 16–19 OP4 20–23 OP5 24–27 OP6 28–31 OP7 FCM operation codes. OP0 is executed first, followed by OP1, through to OP7.
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Enhanced Local Bus Controller 10.3.1.20 Flash Block Address Register (FBAR) The local bus Flash block address register (FBAR), shown in Figure 10-24, locates the NAND Flash block index for the page currently accessed. Offset 0x0_50EC Access: Read/Write 0 7 R 8 31 — W BLK Reset All zeros Figure 10-24. Flash Block Address Register Table 10-27 describes FBAR fields. Table 10-27. FBAR Field Descriptions Bits Name 0–7 — 8–31 BLK Description Reserved Flash block address.
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Enhanced Local Bus Controller Table 10-28 describes FPAR fields for small page devices. Table 10-28. FPAR Field Descriptions, Small Page Device (ORx[PGS] = 0) Bits Name Description 0–16 — Reserved 17–21 PI Page index. PI indexes the page in NAND Flash EEPROM at the current block defined by FBAR, and locates the corresponding transfer buffer in the FCM buffer RAM.
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Enhanced Local Bus Controller 10.3.1.22 Flash Byte Count Register (FBCR) The local bus Flash byte count register (FBCR), shown in Figure 10-27, defines the size of FCM block transfers for reads and writes to the NAND Flash EEPROM. Offset 0x0_50F4 Access: Read/Write 0 19 20 R 31 — W BC Figure 10-27. Flash Byte Count Register Table 10-30 describes FBCR fields. Table 10-30.
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Enhanced Local Bus Controller Table 10-31. FECCn Field Descriptions Bits Name 0 V Valid bit. This bit denotes that the ECC stored in this register is valid. It is set for full page write/read transfers if ECC generation/checking is enabled in BRn[DECC]. 1–7 — Reserved 8–31 ECC 10.4 Description 24 bit ECC; For nth 512 bytes of a page in case of large page or for (4k + n)th 512 byte page for small page where k = 0,1,2,...). It stores calculated ECC value during writes/reads.
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Enhanced Local Bus Controller Internal Memory Access Request Select 32-bit System Address Address Comparator Bank Select UPM A/B/C FCM buffer RAM MSEL Field GPCM FCM Signals Timing Generator 32-bit Physical RAM Address (A) External Signals Figure 10-29. Basic Operation of Memory Controllers in the eLBC Each memory bank (chip select) can be assigned to any of these three types of machines through the machine select bits of the base register for that bank (BRn[MSEL]), as illustrated in Figure 10-29.
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Enhanced Local Bus Controller LCLK LCS LWE LA[0:25] 5420 5421 5422 5423 543C 543D 543E 543F LD[0:15] D[B0] D[B1] D[B2] D[B3] DB[28] D[B29] D[B30] D[B31] Note: All address and signal values are shown in hexadecimal. D[Bk] = kth of 32 data bytes. Figure 10-30. Example of 8-Bit GPCM Writing 32 Bytes to Address 0x5420 (LCRR[PBYP] = 0) 10.4.1.
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Enhanced Local Bus Controller are pending, LBCTL is asserted (high) one bus clock cycle before the next transaction starts to allow a whole bus cycle for the bus to turn around before the next address is driven. 10.4.1.4 Bus Monitor A bus monitor is provided to ensure that each bus cycle is terminated within a reasonable (user defined) period. When a transaction starts, the bus monitor starts counting down from the time-out value (LBCR[BMT] × LBCR[BMTPS]) until a data beat is acknowledged on the bus.
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Enhanced Local Bus Controller memory cycle are taken from ORn. These attributes include the CSNT, ACS, XACS, SCY, TRLX, EHTR and SETA fields. LCLK LD Read Data LA TA Valid Address ACS=10 ACS=11 LCSn LOE Figure 10-33. GPCM Basic Read Timing (XACS = 0, ACS = 1x, TRLX = 0, CLKDIV = 4,8) 10.4.2.1 GPCM Read Signal Timing The basic GPCM read timing parameters that may be set by the ORn attributes are shown in Figure 10-34.
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Enhanced Local Bus Controller Table 10-32 lists the signal timing parameters for a GPCM read access as the option register attributes are varied. Table 10-32.
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Enhanced Local Bus Controller 10.4.2.2 GPCM Write Signal Timing The basic GPCM write timing parameters that may be set by the ORn attributes are shown in Figure 10-35. The write access cycle commences upon latching of the memory address, and concludes when LCSn returns high. LBCTL remains stable for the entire cycle to drive data onto any secondary data bus. Write data becomes invalid following the falling edge of TA.
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Enhanced Local Bus Controller Table 10-33.
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Enhanced Local Bus Controller • • Two clock cycles later (for LCRR[CLKDIV] = 2, 4, or 8), when ORn[XACS] = 1. Three clock cycles later (for LCRR[CLKDIV] = 2, 4, or 8), when ORn[XACS] = 1 and ORn[TRLX] = 1. The timing diagram in Figure 10-33 shows two chip-select assertion timings for the case LCRR[CLKDIV] = 4 or 8. If LCRR[CLKDIV] = 2, LCSn asserts identically for ORn[ACS] = 10 or 11. 10.4.2.3.1 Programmable Wait State Configuration The GPCM supports internal generation of transfer acknowledge.
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Enhanced Local Bus Controller example, when ACS = 00 and CSNT = 1, LWEn is negated one quarter of a clock earlier, as shown in Figure 10-36. If LCRR[CLDIV] = 2, LWEn is negated coincident with LCSn. 1. LCSn is affected by CSNT and TRLX only if ACS[0] is non zero. However, LWEn is affected independent of ACS. 2. When CSNT attribute is asserted, the strobe is negated one quarter of a clock before the normal case provided that LCRR[CLDIV] = 4 or 8. 3.
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Enhanced Local Bus Controller LCLK LA Address1 LD Address2 Read Data ACS=10 TA Bus Turnaround ACS=11 LCSn Extended Hold Time LBCTL LWEn SCY=1,TRLX=1 LOE Figure 10-37. GPCM Relaxed Timing Back-to-Back Reads (XACS = 0, ACS = 1x, SCY = 1, CSNT = 0, TRLX = 1, EHTR = 0, CLKDIV = 4, 8) LCLK LA Address1 LD Address2 Write Data1 ACS=10 TA ACS=11 Write Data2 ACS=10 LCSn LBCTL LWEn LOE Figure 10-38.
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Enhanced Local Bus Controller When TRLX and CSNT are set in a write access, the LWE[0:1] strobe signals are negated one clock earlier than in the normal case, as shown in Figure 10-39 and Figure 10-40. If ACS 00, LCSn is also negated one clock earlier. LCLK LA Address LD TA Write Data ACS=10 CSNT=1 LCSn LBCTL LWEn LOE Figure 10-39.
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Enhanced Local Bus Controller with the assertion of LCSn) by programming TRLX = 1. LOE negates on the rising clock edge coinciding with LCSn negation 10.4.2.3.5 Extended Hold Time on Read Accesses Slow memory devices that take a long time to disable their data bus drivers on read accesses should choose some combination of ORn[TRLX,EHTR].
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Enhanced Local Bus Controller 10.4.2.4 External Access Termination (LGTA) External access termination is supported by the GPCM using the asynchronous LGTA input signal, which is synchronized and sampled internally by the local bus. If, during assertion of LCSn, the sampled LGTA signal is asserted, it is converted to an internal generation of transfer acknowledge, which terminates the current GPCM access (regardless of the setting of ORn[SETA]).
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Enhanced Local Bus Controller Table 10-34. Boot Bank Field Values after Reset for GPCM as Boot Controller Register Field Setting BR0 BA 0000_0000_0000_0000_0 PS From RCWH[ROMLOC], RLEXT = 0 DECC 00 WP 0 MSEL 000 V 1 AM 0000_0000_0000_0000_0 BCTLD 0 CSNT 1 ACS 11 XACS 1 SCY 1111 SETA 0 TRLX 1 EHTR 1 OR0 10.4.3 Flash Control Machine (FCM) The FCM provides a glueless interface to parallel-bus NAND Flash EEPROM devices.
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Enhanced Local Bus Controller LCSn CE LFCLE CLE LFALE ALE LFWE0 WE LFRE RE 8-bit NAND Flash EEPROM 3.3V eLBC in FCM Mode 4.7K LFRB RDY/BSY LFWP WP LA LD[0:7] N.C. IO[7:0] LD[8:15] N.C. Figure 10-44. Local Bus to 8-Bit FCM Device Interface Basic read access timing for FCM is shown in Figure 10-45. Although LCLK is shown for reference, NAND Flash EEPROMs do not make use of the clock.
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Enhanced Local Bus Controller FCM asserts LCSn to commence a command sequence to the Flash device. After a delay of tCSCT, the first command can be written to the device on assertion of LFWE0, followed by any parameters (typically address bytes and data), and concluded with a secondary command. In many cases, the second command initiates a long-running operation inside the Flash device, which pulls the wired-OR pin LFRB low to indicate that the device is busy.
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Enhanced Local Bus Controller numbered P is associated with buffer number (P mod 8), where P = FPAR[PI]. Since the bank size set by ORn[AM] will be greater than 8 Kbytes, an identical image of the FCM buffer RAM appears replicated every 8 Kbytes throughout the bank address space. It is recommended that the bank size be set to 32 Kbytes, which covers a single NAND Flash block for small-page devices. For FCM commands, register FPAR sets the page address and, therefore, also the buffer number.
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Enhanced Local Bus Controller starting address in either the main region (MS = 0) or the spare region (MS = 1). Where different eLBC banks control both small and large-page devices, a large-page 4 Kbyte buffer must be assigned to either the first 4 or last 4 small-page buffers.
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Enhanced Local Bus Controller The placement of ECC code words in relation to FMR[ECCM] is shown in Figure 10-49. For small-page devices, only a single 512-byte main region is ECC-protected. For large-page devices, there are four adjacent main regions, and each has a 16-byte spare region—of which only one is shown in the figure.
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Enhanced Local Bus Controller FIR Register parallel load on FCM bank select OP0 OP1 OP2 OP4 OP5 OP6 OP7 NOP Flash instruction shift register 4 bits FMR Register OP3 FCM Instruction Buffer FCR Register op-code 4 bits data 8 bits FBAR Register FPAR Register NAND Flash Bus Signal Generator FBCR Register MDR Register MDR AS select LD[0:7] LFWE0 LFCLE LFALE LFRE LFRB LFWP Figure 10-50. FCM Instruction Sequencer Mechanism 10.4.3.2.
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Enhanced Local Bus Controller 10.4.3.2.3 FCM Address Instructions Address instructions are used to issue addresses to the NAND Flash EEPROM. A complete device address is formed from a sequence of one or more bytes, each written onto LD[0:7] with LFALE and LFWE0 asserted together. There are three kinds of address generation provided: • Column address—CA.
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Enhanced Local Bus Controller instruction. Sampling and time-outs for polling the LFRB pin follow the behavior of CWn instructions. 10.4.3.2.5 FCM Data Write Instructions Data write instructions assert LFWE0 repeatedly (with LFCLE and LFALE both negated) to transfer one or more bytes of write data to the NAND Flash EEPROM. Data write instructions are distinguished by their data source: • Write data from FCM buffer RAM—WB.
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Enhanced Local Bus Controller LCLK (unused) write cycle #1 LFCLE/ LFALE write cycle #2 tWP tADL tWS LFWE0 tCST tCHT tWC write data command/address LD[0:7] TA Notes: tCST = Command to LFWE0 set-up time. tWP = LFWE0 pulse time, driven low. tCHT = Command to LFWE0 hold time. tWS = Command wait state time. tADL = Command/address to write data delay. tWC = Command cycle time. Figure 10-51.
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Enhanced Local Bus Controller LCLK (unused) LFCLE LFALE LFWE0 LD[0:7] command address 0 address 1 address 2 TA Figure 10-52. Example of FCM Command and Address Timing with Minimum Delay Parameters (for TRLX = 0, CHT = 0, CST = 0, SCY = 0, CLKDIV = 4*N) An example of relaxed command timing is shown in Figure 10-53. LCLK (unused) LFCLE 2×SCY = 4 cycles LFALE LFWE0 command LD[0:7] address TA Figure 10-53.
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Enhanced Local Bus Controller LFCLE long-latency CW command issue LFWE ready state NAND FlashFlash busy state LFRB TRLX = 0: TRLX = 1: LFRB sample points 16×(2+SCY) LCLK cycles FCM continues following LFRB high 8×(2+SCY) cycles LFRE Figure 10-54. FCM Delay Prior to Sampling LFRB State 10.4.3.3.4 FCM Read Data Timing The timing for read data transfers is shown in Figure 10-55. Upon assertion of LFRE, the Flash device will enable its output drivers and drive valid read data while LFRE is held low.
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Enhanced Local Bus Controller The timing parameters are summarized in Table 10-37. Table 10-37. FCM Read Data Timing Parameters Option Register Attributes 1 10.4.3.3.5 Timing Parameter (LCLK Clock Cycles)1 TRLX RST tRP tRHT tWS tRC tWRT 0 0 ¾+SCY 1 SCY 2+SCY 4×(2+SCY) 0 1 1+SCY 1 SCY 2+SCY 4×(2+SCY) 1 0 ½+2×SCY 2 2×SCY 3+2×SCY 8×(2+SCY) 1 1 1+2×SCY 2 2×SCY 3+2×SCY 8×(2+SCY) In the parameters, SCY refers to a delay of ORn[SCY] clock cycles.
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Enhanced Local Bus Controller When the core begins accessing memory after system reset, LCS0 is asserted initially to load a 4-Kbyte boot block into the FCM buffer RAM, but core instruction fetches occur from the buffer RAM. 10.4.3.4.1 FCM Bank 0 Reset Initialization The boot chip-select also provides a programmable port size, which is configured during reset. The boot chip-select does not provide write protection.
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Enhanced Local Bus Controller Bank Base Address boot block buffer 4096-byte boot block —no NAND Flash spare regions offset 0x1000 replicated FCM buffer RAM images in bank End of Bank Figure 10-57. FCM Buffer RAM Memory Map During Boot Loading The process for booting is as follows: 1. Following negation of PORESET, eLBC is released from reset and commences automatic boot block loading if FCM is selected as the boot ROM location.
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Enhanced Local Bus Controller 6. The CPU now commences fetching instructions, in random order, from the FCM buffer RAM. This first-level boot loader typically copies a secondary boot loader into system memory, and continues booting from there. Boot software must clear FMR[BOOT] to enable normal operation of FCM. 10.4.4 User-Programmable Machines (UPMs) UPMs are flexible interfaces that connect to a wide range of memory devices.
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Enhanced Local Bus Controller The RAM array contains 64 words of 32-bits each. The signal timing generator loads the RAM word from the RAM array to drive the general-purpose lines, byte-selects, and chip-selects. If the UPM reads a RAM word with WAEN set, the external LUPWAIT signal is sampled and synchronized by the memory controller and the current request is frozen. 10.4.4.1 UPM Requests A special pattern location in the RAM array is associated with each of the possible UPM requests.
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Enhanced Local Bus Controller Table 10-39. UPM Routines Start Addresses (continued) UPM Routine 10.4.4.1.1 Routine Start Address Refresh timer (RTS) 0x30 Exception condition (EXS) 0x3C Memory Access Requests The user must ensure that the UPM is appropriately initialized before a request occurs. The UPM supports two types of memory reads and writes: • A single-beat transfer transfers one operand consisting of up to a single word (dependent on port size).
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Enhanced Local Bus Controller 10.4.4.1.3 Software Requests—RUN Command Software can start a request to the UPM by issuing a RUN command to the UPM. Some memory devices have their own signal handshaking protocol to put them into special modes, such as self-refresh mode. For these special cycles, the user creates a special RAM pattern that can be stored in any unused areas in the UPM RAM. Then a RUN command is used to run the cycle.
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Enhanced Local Bus Controller – Since the result of any update to the MxMR/MDR register must be in effect before the dummy read or write to the UPM region, a write to MxMR/MDR should be followed immediately by a read of MxMR/MDR. – The UPM memory region should have the same MMU settings as the memory region containing the MxMR configuration register; both should be mapped by the MMU as cache-inhibited and guarded. This prevents the CPU from re-ordering a read of the UPM memory around the read of MxMR.
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Enhanced Local Bus Controller illustrates the steps required to perform two reads from the RAM array at non-sequential addresses assuming that the relevant BRn and ORn registers have been previously set up: 1. Program MxMR for the first read with the desired RAM array address. 2. Read MxMR to ensure that the MxMR has already been updated with the desired configuration, such as RAM array address. 3. Perform a dummy read transaction. 4. Read/check MxMR[MAD].
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Enhanced Local Bus Controller LCLK T1 T2 T3 T4 Figure 10-62. UPM Clock Scheme for LCRR[CLKDIV] = 4 or 8 10.4.4.4 RAM Array The RAM array for each UPM is 64 locations deep and 32 bits wide, as shown in Figure 10-63. The signals at the bottom of the figure are UPM outputs. The selected LCSn is for the bank that matches the current address. The selected LBS is for the byte lanes read or written by the access.
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Enhanced Local Bus Controller 0 R W 1 2 3 4 5 6 7 8 CST1 CST2 CST3 CST4 BST1 BST2 BST3 BST4 Reset 9 G0L 10 11 G0H 12 13 14 15 G1T1 G1T3 G2T1 G2T3 28 29 30 31 NA UTA All zeros 16 17 18 R 19 20 21 G4T1/ G4T3/ G3T1 G3T3 G5T1 G5T3 DLT3 WAEN W Reset 22 23 REDO 24 25 LOOP EXEN 26 27 AMX TODT LAST All zeros Figure 10-64. RAM Word Fields Table 10-40 contains descriptions of the RAM word fields. Table 10-40.
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Enhanced Local Bus Controller Table 10-40. RAM Word Field Descriptions (continued) Bits Name Description 10–11 G0H General purpose line 0 higher. Defines the state of LGPL0 during the bus clock quarter phases 3 and 4 (second half phase). 00 Value defined by MxMR[G0CL] 01 Reserved 10 0 11 1 12 G1T1 General purpose line 1 timing 1. Defines the state (0 or 1) of LGPL1 during bus clock quarter phases 1 and 2 (first half phase). 13 G1T3 General purpose line 1 timing 3.
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Enhanced Local Bus Controller Table 10-40. RAM Word Field Descriptions (continued) Bits Name Description 24 LOOP Loop start/end. The first RAM word in the RAM array where LOOP is 1 is recognized as the loop start word. The next RAM word where LOOP is 1 is the loop end word. RAM words between, and including the start and end words, are defined as part of the loop. The number of times the UPM executes this loop is defined in the corresponding loop fields of the MxMR.
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Enhanced Local Bus Controller Table 10-40. RAM Word Field Descriptions (continued) Bits Name Description 31 LAST Last word. When LAST is read in a RAM word, the current UPM pattern terminates and control signal timing set in the RAM word is applied to the current (and last) cycle.
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Enhanced Local Bus Controller Bank Selected LA[23:25] Byte count BRn[MSEL] BRn[PS] UPMA LBS0 UPMB MUX Byte-Select Logic LBS1 UPMC Figure 10-66. LBS Signal Selection The uppermost byte select (LBS0), when asserted, indicates that LD[0:7] contains valid data during a cycle. Likewise, LBS1 indicates that LD[8:15] contain valid data. For a UPM refresh timer request, all LBS[0:1] signals are asserted/negated by the UPM according to the refresh pattern only.
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Enhanced Local Bus Controller Table 10-41. MxMR Loop Field Use Request Serviced 10.4.4.4.6 Loop Field Read single-beat cycle RLF Read burst cycle RLF Write single-beat cycle WLF Write burst cycle WLF Refresh timer expired TLF RUN command RLF Repeat Execution of Current RAM Word (REDO) The REDO function is useful for wait-state insertion in a long UPM routine that would otherwise need too many RAM words.
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Enhanced Local Bus Controller Table 10-42 shows how the RAM word AMX bits and MxMR[AM] settings can be used to affect row × column address multiplexing on the LA[10:25] signals. NOTE Multiple-bank DRAM and SDRAM devices require that the bank address be driven during both RAS and CAS cycles. The UPM does not support a persistent bank address on both RAS and CAS cycles. Therefore, external logic must be used to supply a bank address to these devices. Table 10-42.
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Enhanced Local Bus Controller 10.4.4.4.8 Data Valid and Data Sample Control (UTA) When a read access is handled by the UPM, and the UTA bit is 1 (data is to be sampled by the eLBC), the value of the DLT3 bit in the same RAM word, in conjunction with MxMR[GPL4], determines when the data input is sampled by the eLBC as follows: • If MxMR[GPL4] = 1 (G4T4/DLT3 functions as DLT3) and DLT3 = 1 in the RAM word, data is latched on the falling edge of the bus clock instead of the rising edge.
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Enhanced Local Bus Controller Synchronization of LUPWAIT starts at the rising edge of the bus clock and takes at least 1 bus cycle to complete. If LUPWAIT is asserted and WAEN = 1 in the current UPM word, the UPM is frozen until LUPWAIT is negated. The value of external signals driven by the UPM remains as indicated in the previous RAM word. When LUPWAIT is negated, the UPM continues normal functions. Note that during WAIT cycles, the UPM does not handle data.
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Enhanced Local Bus Controller 10.4.4.6 Extended Hold Time on Read Accesses Slow memory devices that take a long time to turn off their data bus drivers on read accesses should choose some non-zero combination of ORn[TRLX] and ORn[EHTR]. The next accesses after a read access to the slow memory device is delayed by the number of clock cycles specified in the ORn register in addition to any existing bus turnaround cycle. 10.5 Initialization/Application Information 10.5.
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Enhanced Local Bus Controller 10.5.2 Interface to Different Port-Size Devices The eLBC supports 8- and 16-bit data port sizes. However, the bus requires that the portion of the data bus used for a transfer to or from a particular port size be fixed. A 16-bit port must reside on LD[0:15], and an 8-bit port must reside on LD[0:7]. The local bus always tries to transfer the maximum amount of data on all bus cycles. Figure 10-71 shows the device connections on the data bus.
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Enhanced Local Bus Controller Table 10-43. Data Bus Drive Requirements For Read Cycles (continued) Port Size/LD Data Bus Assignments Transfer Size Half Word Word 1 10.5.3 Address State 1 3 lsbs 16-Bit 16–23 8-Bit 0–7 8–15 24–31 0–7 000 OP0 OP1 OP0 001 — OP1 OP1 010 OP2 OP3 OP2 100 OP4 OP5 OP4 101 — OP5 OP5 110 OP6 OP7 OP6 000 OP0 OP1 OP0 100 OP4 OP5 OP4 8–15 16–23 24–31 Address state is the calculated address for port size.
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Enhanced Local Bus Controller Table 10-44. FCM Register Settings for Soft Reset (ORn[PGS] = 1) (continued) 10.5.3.2 Register Initial Contents MDR — FIR 0x40000000 Description unused OP0 = CM0 = command 0; OP1–OP7 = NOP NAND Flash Read Status Command Sequence Example An example of configuring FCM to execute a status read command to large-page NAND Flash is shown in Table 10-45. This sequence does not require use of the shared FCM buffer RAM, but reads the NAND Flash status into register MDR[AS0].
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Enhanced Local Bus Controller Table 10-46. FCM Register Settings for ID Read (ORn[PGS] = 1) (continued) 10.5.3.
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Enhanced Local Bus Controller operation to the bank. At the conclusion of the sequence, eLBC will issue a command complete interrupt (LTESR[CC]) if interrupts are enabled. Note that operations specified by OP3 and OP4 (status read) should never be skipped while erasing a NAND Flash device, because, in case that happens, contention may arise on LGPL4.
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Enhanced Local Bus Controller Table 10-49. FCM Register Settings for Page Program (ORn[PGS] = 1) 10.5.
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Enhanced Local Bus Controller Figure 10-72 shows single-beat read access to FPM DRAM. LCLK LD Read Data A Column Row TA LA Row lsb’s Column lsb’s LCSn (RAS) LBSn (CAS) LGPL1 (R/W) LBCTL Figure 10-72. Single-Beat Read Access to FPM DRAM Table 10-50 lists UPM code for single-beat read access. Table 10-50.
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Enhanced Local Bus Controller Table 10-50. UPM Code for Single-Beat Read Access (continued) g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t3 Bit 21 redo[0] Bit 22 redo[1] Bit 23 loop 0 0 0 Bit 24 exen 0 0 0 Bit 25 amx0 1 0 0 Bit 26 amx1 0 0 0 Bit 27 na 0 0 0 Bit 28 uta 0 0 1 Bit 29 todt 0 0 1 Bit 30 last 0 0 1 Bit 31 RSS + 1 RSS + 2 RSS RSS + 1 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev.
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Enhanced Local Bus Controller Figure 10-73 shows single-beat write access to FPM DRAM. LCLK LD Write Data A Row Write Data Column TA LA Row lsb’s Column lsb’s LCSn (RAS) LBSn (CAS) LGPL1 (R/W) LBCTL Figure 10-73. Single-Beat Write Access to FPM DRAM Table 10-51 lists UPM code for single-beat write access. Table 10-51.
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Enhanced Local Bus Controller Table 10-51. UPM Code for Single-Beat Write Access (continued) g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t3 Bit 21 redo[0] Bit 22 redo[1] Bit 23 loop 0 0 0 Bit 24 exen 0 0 0 Bit 25 amx0 1 0 0 Bit 26 amx1 0 0 0 Bit 27 na 0 0 0 Bit 28 uta 0 0 1 Bit 29 todt 0 0 1 Bit 30 last 0 0 1 Bit 31 WSS + 1 WSS + 2 WSS WSS + 1 MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev.
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Enhanced Local Bus Controller Figure 10-74 shows burst read access write access to FPM DRAM using LOOP. LCLK LD Data 2 Data 1 A Column 1 Row Column 2 TA LA Row lsb’s Column 1 lsb’s Column 2 lsb’s LCSn (RAS) LBSn (CAS) LGPL1 (R/W) LBCTL Figure 10-74. Burst Read Access to FPM DRAM Using LOOP (Two Beats) Table 10-52 lists UPM code for burst read access. Table 10-52.
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Enhanced Local Bus Controller Table 10-52.
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Enhanced Local Bus Controller Figure 10-75 shows refresh cycle (CBR) to FPM DRAM. LCLK LD A TA LA LCSn (RAS) LBSn (CAS) LBCTL Figure 10-75. Refresh Cycle (CBR) to FPM DRAM Table 10-53 lists UPM code for refresh cycle. Table 10-53.
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Enhanced Local Bus Controller Table 10-53. UPM Code for Refresh Cycle (continued) g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t3 Bit 21 redo[0] Bit 22 redo[1] Bit 23 loop 0 0 0 Bit 24 exen 0 0 0 Bit 25 amx0 0 0 0 Bit 26 amx1 0 0 0 Bit 27 na 0 0 0 Bit 28 uta 0 0 0 Bit 29 todt 0 0 1 Bit 30 last 0 0 1 Bit 31 PTS PTS + 1 PTS + 2 Figure 10-76 shows exception cycle. LCLK LD TA LCSn (RAS) LBSn (CAS) LBCTL Figure 10-76.
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Enhanced Local Bus Controller Table 10-54 lists UPM code for exception cycle. Table 10-54.
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Enhanced Local Bus Controller 10.5.5 Interfacing to ZBT SRAM Using UPM ZBT SRAMs have been designed to optimize the performance of table access in networking applications. This section describes how to interface to ZBT SRAMs. Figure 10-77 shows the connections. The UPM is used to generate control signals. The same interfacing is used for pipelined and flow-through versions of ZBT SRAMs. However different UPM patterns must be generated for those cases.
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Enhanced Local Bus Controller The UPM also supports single beat accesses. Because the ZBT SRAM does not support this and always responds with a burst, the UPM pattern has to take care that data for the critical beat is provided (for write) or sampled (for read), and that the rest of the burst is ignored (by negating WE). The UPM controller basically has to wait for the end of the SRAM burst to avoid bus contention with further bus activities.
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Enhanced Local Bus Controller MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev.
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Chapter 11 Enhanced Secure Digital Host Controller 11.1 Overview The enhanced secure digital host controller (eSDHC) provides an interface between the host system and these types of memory cards: • Multi Media card (MMC) MMC is a universal low-cost data storage and communication medium designed to cover a wide area of applications including mobile video and gaming, which are available from either pre-loaded MMCs or downloadable from cellular phones, WLAN, or other wireless networks.
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Enhanced Secure Digital Host Controller The eSDHC acts as a bridge, passing host bus transactions to SD card/SDIO/MMCs by sending commands and performing data accesses to or from the cards. It handles the SD/SDIO/MMC protocol at the transmission level. Figure 11-1 shows connection of the eSDHC. MPC8308 MMC/SD/SDIO/ Host Controller MMC Transceiver Register Bank DMA Interface CSB Bus SD Card Card Slot SDIO Card Power Supply Register Bus Figure 11-1.
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Enhanced Secure Digital Host Controller Figure 11-2 is a block diagram of the eSDHC.
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Enhanced Secure Digital Host Controller • • • • • • • • • • • • • • • — SD Card Specification, Part E1, SD Input/Output (SDIO) Card Specification, Version 2.
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Enhanced Secure Digital Host Controller Table 11-1 shows the properties of the eSDHC I/O signals. Table 11-1. Signal Properties Name Port SD_CLK O SD_CMD I/O Command line to card High impedance Pull up SD_DAT3 I/O 4-bit mode: DAT3 line or configured as card detection pin 1-bit mode: May be configured as card detection pin High impedance Board should have 100-K pull down. The card drives 50-K pull up as required by the SD Card Specification.
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Enhanced Secure Digital Host Controller Table 11-2. eSDHC Memory Map eSDHC Registers—Block Base Address 0x2_E000 Offset 1 Register Access Reset Section/Page 0x000 DMA system address (DSADDR) R/W 0x0000_0000 11.4.1/11-7 0x004 Block attributes (BLKATTR) R/W 0x0001_0000 11.4.2/11-7 0x008 Command argument (CMDARG) R/W 0x0000_0000 11.4.3/11-8 0x00C Command transfer type (XFERTYP) R/W 0x0000_0000 11.4.4/11-9 0x010 Command response0 (CMDRSP0) R 0x0000_0000 11.4.
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Enhanced Secure Digital Host Controller 11.4.1 DMA System Address Register (DSADDR) The DMA system address register contains the system memory address used for DMA transfers. Only access this register when no transactions are executing (after transactions have stopped). The host driver should wait until PRSSTAT[DLA] is cleared. Figure 11-3 shows the DMA system address register.
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Enhanced Secure Digital Host Controller Table 11-4 describes the BLKATTR fields. Table 11-4. BLKATTR Field Descriptions Bit Name 0–15 Description BLKCNT Block count for current transfer. This field is enabled when XFERTYP[BCEN] is set and is valid only for multiple block transfers. The host driver should set this field to a value between 1 and the maximum block count. The eSDHC decrements the block count after each block transfer and stops when the count reaches zero.
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Enhanced Secure Digital Host Controller Table 11-5 describes the CMDARG fields. Table 11-5. CMDARG Field Descriptions Bit Name 0–31 11.4.4 Description CMDARG Command argument. The SD/MMC command argument is specified as bits 39–8 of the command format in the SD or MMC Specification. If PRSSTAT[CMD] is set, this register is write-protected. Transfer Type Register (XFERTYP) The transfer type register, shown in Figure 11-6, controls the operation of data transfers.
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Enhanced Secure Digital Host Controller Table 11-6. XFERTYP Field Descriptions (continued) Bit Name Description 8–9 CMDTYP Command type. There are three types of special commands: suspend, resume, and abort. Clear this bit field for all other commands. • Suspend command. If the suspend command succeeds, the eSDHC assumes the SD bus has been released and it is possible to issue the next command which uses the SD_DAT line.
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Enhanced Secure Digital Host Controller Table 11-6. XFERTYP Field Descriptions (continued) Bit Name Description 14–15 RSPTYP 16–25 — 26 MSBSEL Multi/single block select. Enables multiple block SD_DAT line data transfers. For any other commands, this bit should be cleared. If this bit is cleared, it is not necessary to set the block count register. (Refer to Table 11-7.) 0 Single block 1 Multiple blocks 27 DTDSEL Data transfer direction select.
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Enhanced Secure Digital Host Controller Table 11-8 shows how the response type can be determined by the command index check enable, command CRC check enable, and response type bits. Table 11-8. Relation Between Parameters and Name of Response Type Response Type XFERTYP[RSPTYP] Index Check Enable XFERTYP[CICEN] CRC Check Enable XFERTYP[CCCEN] Response Type 00 0 0 No Response 01 0 1 R2 10 0 0 R3, R4 10 1 1 R1, R5, R6 11 1 1 R1b, R5b • • 11.4.
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Enhanced Secure Digital Host Controller Table 11-9 describes the mapping of command responses from the SD bus to the command response registers for each response type. In the table, R[ ] refers to a bit range within the response data as transmitted on the SD bus. Table 11-9.
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Enhanced Secure Digital Host Controller 11.4.6 Buffer Data Port Register (DATPORT) The buffer data port register, shown in Figure 11-8, is a 32-bit data port register used to access the internal buffer. NOTE When the internal DMA is not enabled and a write transaction is in operation, DATPORT must not be read. DATPORT also must not be used to read (or write) data by the CPU if the data will be written (or read) by the eSDHC internal DMA.
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Enhanced Secure Digital Host Controller 11.4.7 Present State Register (PRSSTAT) The present state register (PRSSTAT), shown in Figure 11-9, indicates the status of the eSDHC to the host driver.
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Enhanced Secure Digital Host Controller Table 11-11. PRSSTAT Field Descriptions (continued) Bit Name Description 13 CDPL Card detect pin level. This bit reflects the inverse value of the SD_CD pin for the card socket. Debouncing is not performed on this bit. This bit may be valid, but it is not guaranteed because of a propagation delay. Use of this bit is limited to testing since it must be debounced by software. A software reset does not affect this bit.
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Enhanced Secure Digital Host Controller Table 11-11. PRSSTAT Field Descriptions (continued) Bit Name Description 23 WTA Write transfer active. This status indicates a write transfer is active. If this bit is 0, it means no valid write data exists in eSDHC. This bit is set in either of the following cases: • After the end bit of the write command. • When writing a 1 to PROCTL[CREQ] to restart a write transfer.
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Enhanced Secure Digital Host Controller Table 11-11. PRSSTAT Field Descriptions (continued) Bit Name 29 DLA Description Data line active. Indicates whether one of the SD_DAT line on SD bus is in use. For read transactions, this bit indicates if a read transfer is executing on the SD bus. Clearing this bit from 1 to 0 between data blocks generates a block gap event interrupt.
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Enhanced Secure Digital Host Controller NOTE The host driver can issue CMD0, CMD12, CMD13 (for memory) and CMD52 (for SDIO) when the SD_DAT lines are busy during a data transfer. These commands can be issued when PRSSTAT[CIHB] is cleared. Other commands should be issued when PRSSTAT[CDIHB] is cleared. Possible changes to the SD Physical Specification may add other commands to this list in the future. 11.4.8 Protocol Control Register (PROCTL) The protocol control register is shown in Figure 11-10.
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Enhanced Secure Digital Host Controller Table 11-12. PROCTL Field Descriptions (continued) Bit Name Description 12 IABG Interrupt at block gap. This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle. If the SDIO card cannot signal an interrupt during a multiple block transfer, this bit should be cleared to avoid an inadvertent interrupt. When the host driver detects an SDIO card insertion, it should set this bit according to the CCCR of the card.
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Enhanced Secure Digital Host Controller Table 11-12. PROCTL Field Descriptions (continued) Bit Name Description 25 CDTL 26–27 EMODE Endian mode. eSDHC supports only address-invariant mode in data transfer. 00 Reserved 01 Reserved 10 Address-invariant mode. Each byte location in the main memory is mapped to the same byte location in the MMC/SD card. 11 Reserved 28 D3CD SD_DAT3 as card detection pin. If this bit is set, SD_DAT3 should be pulled down to act as a card detection pin.
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Enhanced Secure Digital Host Controller 11.4.9 System Control Register (SYSCTL) The system control register is shown in Figure 11-11. Offset: 0x02C (SYSCTL) 0 Access: Mixed 3 4 5 6 7 8 11 12 15 R — INITA W Reset — DTOCV RSTD RSTC RSTA 0 0 0 0 0 0 0 16 0 0 23 24 0 0 0 0 0 0 0 27 28 29 30 31 R SDCLKFS CLKE PEREN HCKEN IPGEN N DVS W Reset 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Figure 11-11.
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Enhanced Secure Digital Host Controller Table 11-13. SYSCTL Field Descriptions (continued) Bit Name Description 7 RSTA Software reset for all. This reset affects the entire host controller except for the card-detection circuit. Register bits of type Read only, Read/Write, Read only: write-1-to-clear, and Read/Write Automatic clear are cleared. During its initialization, the host driver should set this bit to reset the eSDHC.
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Enhanced Secure Digital Host Controller Table 11-13. SYSCTL Field Descriptions (continued) Bit Name Description 28 CLKEN SD Card Clock Enable 0 Disable the clock 1 Enable the clock 29 PEREN Peripheral clock enable. If set, the peripheral clock is always active and no automatic gating is applied, thus SD_CLK is active only except auto gating-off during buffer danger. If cleared, the peripheral clock is automatically off when no transaction is on the SD bus.
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Enhanced Secure Digital Host Controller be cleared with a single register write. For a card interrupt (IRQSTAT[CINT]), the card must stop asserting the interrupt before writing one to clear. Otherwise, the CINT bit is set again. Figure 11-12 shows the interrupt status register.
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Enhanced Secure Digital Host Controller Table 11-14. IRQSTAT Field Descriptions (continued) Bit Name Description 10 DCE Data CRC error. Occurs when detecting CRC error when transferring read data on the SD_DAT line or when detecting the write CRC status having a value other than 0b010. 0 No Error 1 Error 11 DTOE 12 CIE 13 CEBE 14 CCE Command CRC error.
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Enhanced Secure Digital Host Controller Table 11-14. IRQSTAT Field Descriptions (continued) Bit Name Description 24 CRM Card removal. This bit is set if PRSSTAT[CINS] changes from 1 to 0. When the host driver writes 1 to this bit to clear it, the status of PRSSTAT[CINS] should be confirmed. Because the card-detect state may be changed when the host driver clears this bit, an interrupt event may not be generated. When this bit is cleared, it is set again if no card is inserted.
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Enhanced Secure Digital Host Controller Table 11-15 below shows that command timeout error has higher priority than command complete. If both bits are set, it can be assumed that the response was not received correctly. Table 11-15.
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Enhanced Secure Digital Host Controller Offset: 0x034 (IRQSTATEN) 0 2 3 R 0 0 4 DMAE SEN — W Reset Access: Read/Write 0 1 6 7 8 9 10 11 12 13 14 15 AC12E SEN — DEBE SEN DCE SEN DTOE SEN CIE SEN CEBE SEN CCE SEN CTOE SEN 0 1 0 1 1 1 1 1 1 1 22 23 24 25 26 27 28 29 30 31 CINT SEN CRM SEN CINS SEN BRR SEN BWR SEN DINT SEN BGE SEN TC SEN CC SEN 1 0 0 1 1 1 1 1 1 — 0 0 16 R — W Reset 0 0 0 0 0 0 0 Figure 11-13.
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Enhanced Secure Digital Host Controller Table 11-18. IRQSTATEN Field Descriptions (continued) Bit Name Description 15 CTOESEN 16–22 — 23 CINTSEN Card interrupt status enable. If this bit is cleared, the eSDHC clears the interrupt request to the system. The card interrupt detection is stopped when this bit is cleared and restarted when this bit is set.
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Enhanced Secure Digital Host Controller 11.4.12 Interrupt Signal Enable Register (IRQSIGEN) IRQSIGEN, shown in Figure 11-14, selects which interrupt status is indicated to the host system as the interrupt. These status bits all share the same interrupt line. Setting any of these bits enables an interrupt generation. The corresponding status register bit generates an interrupt when the corresponding interrupt signal enable bit is set.
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Enhanced Secure Digital Host Controller Table 11-19.
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Enhanced Secure Digital Host Controller 11.4.13 Auto CMD12 Error Status Register (AUTOC12ERR) When IRQSTAT[AC12E] is set, the host driver checks this register to identify what kind of error Auto CMD12 indicated. This register is valid only when IRQSTAT[AC12E] is set. Figure 11-15 shows the auto CMD12 error status register. Offset: 0x03C (AUTOC12ERR) Access: Read 0 23 R 24 CNIB AC12E — 25 26 — 27 28 29 30 31 AC12 AC12 AC12 AC12 AC12 IE CE EBE TOE NE W Reset All zeros Figure 11-15.
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Enhanced Secure Digital Host Controller Table 11-20. AUTOC12ERR Field Descriptions (continued) Bit Name Description 30 AC12TOE Auto CMD12 timeout error. Occurs if no response is returned within 64 SD_CLK cycles from the end bit of the command. If this bit is set, the other error status bits (29–27) are meaningless. 0 No error 1 Time out 31 AC12NE Auto CMD12 not executed.
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Enhanced Secure Digital Host Controller 11.4.14 Host Controller Capabilities (HOSTCAPBLT) The host controller capabilities provide the host driver with information specific to the eSDHC implementation. The value in this register does not change in software reset, and any write to this register is ignored. Figure 11-16 shows the auto CMD12 error status register.
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Enhanced Secure Digital Host Controller Table 11-22. HOSTCAPBLT Field Descriptions (continued) Bit Name Description 13–15 MBL Max block length. Indicates the maximum block size that the host driver can read and write to the buffer in the eSDHC. The buffer should transfer block size without wait cycles. 000 512 bytes 001 1024 bytes 010 2048 bytes 011 4096 bytes 16–31 — Reserved 11.4.15 Watermark Level Register (WML) Figure 11-17 shows the watermark level register.
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Enhanced Secure Digital Host Controller Figure 11-18 shows the force event register.
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Enhanced Secure Digital Host Controller Table 11-24. FEVT Field Descriptions (continued) Bit Name Description 27 FEVTAC12IE 28 FEVTAC12EBE 29 FEVTAC12CE 30 FEVTAC12TOE 31 FEVTAC12NE Force event Auto CMD12 index error. Forces AUTOC12ERR[AC12IE] to set. Force event Auto CMD12 end bit error. Forces AUTOC12ERR[AC12EBE] to set. Force event Auto CMD12 CRC error. Forces AUTOC12ERR[AC12CE] to set. Force event Auto CMD12 time out error. Forces AUTOC12ERR[AC12TOE] to set.
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Enhanced Secure Digital Host Controller 11.5.1 Data Buffer The eSDHC uses one configurable data buffer so that data can be transferred between the internal system bus (register bus or CSB bus) and the SD card in an optimized manner to maximize throughput between the two clock domains (the IP peripheral clock and the master clock). See Figure 11-20 for an illustration of the buffer scheme. The buffer is used as temporary storage for data being transferred between the host system and the card.
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Enhanced Secure Digital Host Controller When the internal DMA is not used (XFERTYP[DMAEN] is not set when the command is sent), and more than WML[WR_WML] number of empty word slots are available and ready for receiving new data, the eSDHC sets the IRQSTAT[BWR]. The buffer write ready interrupt is generated if it is enabled by software. When the internal DMA is used, the eSDHC does not inform the system before all the required number of bytes are transferred and no error is encountered.
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Enhanced Secure Digital Host Controller only restriction is from the external card since it may not support such a large block or a partial block access that is not an integer multiple of 512 bytes. 11.5.1.4 Dividing Large Data Transfer This SDIO command CMD53 definition limits the maximum data size of data transfers according to the following formula: Maximum data size = (block size)  (block count) Eqn. 11-2 The length of a multiple block transfer must be in block size units.
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Enhanced Secure Digital Host Controller System Address CSB Interface R/W Indication eSDHC Registers Error Indication Master Logic CSB Signal Cluster Burst Length Data Exchange Buffer Control DMA Engine DMA Request Figure 11-22. DMA CSB Interface Block 11.5.2.1 Internal DMA Request If the watermark level is met in the data transfer and the internal DMA is enabled, the data buffer block sends a DMA request to DMA engine.
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Enhanced Secure Digital Host Controller • • • • • Detects bus state on SD_DAT[0] line Monitors interrupt from the SDIO card Asserts read wait signal Gates off SD clock when the buffer announces danger status Detects write-protect state and other functions It consists of four submodules: SD transceiver, SD clock and monitor, command agent and data agent. 11.5.3.1 SD Transceiver In the SD protocol unit, the transceiver is the main control module.
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Enhanced Secure Digital Host Controller Generator polynomial: G(x) = x7 + x3 + 1 M(x) = (first bit)  xn + (second bit)  xn-1 +...+ (last bit)  x0 CRC[6:0] = Remainder [(M(x)  x7)  G(x)] 11.5.3.4 Data Agent The data agent handles the transactions on the four data lines. Moreover, this module also detects the busy state from on SD_DAT[0] line, and generates read wait state by the request from the transceiver.
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Enhanced Secure Digital Host Controller 11.5.6.1 Interrupts in 1-bit Mode In this case, the SD_DAT[1] pin is dedicated to providing the interrupt function. An interrupt is asserted by pulling the SD_DAT[1] low from the SDIO card, until the interrupt service is finished to clear the interrupt. 11.5.6.2 Interrupt in 4-bit Mode As the interrupt and data line 1 share pin 8 in four-bit mode, an interrupt is only sent by the card and recognized by the host during a specific time.
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Enhanced Secure Digital Host Controller • Figure 11-25 (b) for the sequences of software and hardware events that take place during card interrupt handling procedure Start Register Bus IRQ to CPU Enable Card IRQ in Host eSDHC Registers SDIO Interrupt Status SDIO Interrupt Enable Detect & Steer Card IRQ Command/ Response Handling Read IRQ Status Register Disable Card IRQ in Host IRQ Detecting & Steering Interrogate & Service Card IRQ SD Host SDIO Card Clear IRQ0 Clear IRQ1 SDIO Card IRQ Routing Ye
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Enhanced Secure Digital Host Controller communicate with the card, it can enable the clock and start the operation. This can be done by clearing the SCCR[SDHCCM] bits. 11.6 Initialization/Application Information All communication between system and cards are controlled by the host. The host sends commands of two types: broadcast and addressed (point-to-point) commands. Note that eSDHC supports only one SDIO card.
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Enhanced Secure Digital Host Controller For some scenarios, the response timeout is expected. For instance, after all cards respond to CMD3 and go to the standby state, no response to the host when CMD2 is sent. The host driver should manage false errors similar to this with caution. 11.6.
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Enhanced Secure Digital Host Controller The cards are initialized with a default relative card address (RCA = 0x0000) and with a default driver stage register setting (lowest speed, highest driving current capability). After the card is reset, the host needs to validate the voltage range of the card. See Figure 11-27 for the software flow to reset the eSDHC and card. Write ‘1’ to RSTA Bit to Reset eSDHC Send 80 Clocks to Card Send CMD0/CMD52 to Card to Reset Card Voltage Validation Figure 11-27.
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Enhanced Secure Digital Host Controller select a common voltage range or if a notification should be sent to the system when a non-usable cards in the stack is detected.
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Enhanced Secure Digital Host Controller 11.6.2.4 Card Registry Card registry on MMC and SD/SDIO/SD Combo cards are different. For the SD card, the identification process starts at a clock rate lower than 400 KHz and the power voltage higher than 2.7 V, as defined by the card specification. At this time, the SD_CMD line output drives are push-pull drivers instead of open-drain. After the bus is activated, the host requests the card to send their valid operation conditions.
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Enhanced Secure Digital Host Controller send_command(SET_RELATIVE_ADDR, <...>); retrieve RCA from response; } // else if (card is labeled as SD ...) else if (card is labeled as MMC or CE-ATA) { // treat CE-ATA as MMC send_command(ALL_SEND_CID, <...>); rca = 0x1; // arbitrarily set RCA, 1 here for example, this RCA is also the // relative address to access the CE-ATA card send_command(SET_RELATIVE_ADDR, 0x1 << 16, <...>); // send RCA at upper 16 bits } // end of else if (card is labeled as MMC...
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Enhanced Secure Digital Host Controller For simplicity, the software flow described below incorporates the internal DMA, and the write operation is a multi-block write with Auto CMD12 enabled. For the other method (CPU polling status) and different transfer nature, the internal DMA part of the procedure should be removed and alternative steps inserted. 1. Check the card status and wait until the card is ready for data. 2. Set the card block length.
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Enhanced Secure Digital Host Controller 12. Check the status bit to see if a read CRC error or any other errors occurred between sending Auto CMD12 and receiving the response. The number of blocks left during the data transfer is accessible by reading the content of BLKATTR[BLKCNT]. Due to the data transfers and setting PROCTL[SABGREQ] are concurrent, along with the delay of register read and the register setting, the actual number of blocks left may not be the same as the value read earlier.
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Enhanced Secure Digital Host Controller 5. Disable the buffer read ready interrupt, configure the DMA setting, and enable the eSDHC DMA when sending the command with data transfer. Set XFERTYP[AC12EN]. 6. Wait for the transfer complete interrupt. 7. Check the status bit to see if a read CRC error or any other errors occurred between sending Auto CMD12 and receiving the response. 11.6.3.2.2 Read with Pause In general, the read operation is not able to pause.
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Enhanced Secure Digital Host Controller If the suspend command is sent and the transfer is later resumed by means of the resume command, the eSDHC takes the command as a normal one accompanied with data transfer, and it is left for the driver to set all the relevant registers before the transfer is resumed. If there is only one block to send when the transfer is resumed, XFERTYP[MSBSEL, BCEN] and IRQSTT[AC12EN] are set. However, the eSDHC automatically sends CMD12 to mark the end of a multi-block transfer.
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Enhanced Secure Digital Host Controller the transfer. When an error occurs at this point, it is recommended that the host driver responds with one of the following actions (as appropriate to kind of error): 1. Auto CMD12 response timeout. It is not certain whether the command has been accepted by the card or not. The driver should clear the Auto CMD12 error status bits and resend CMD12 until it is accepted by the card. 2. Auto CMD12 response CRC error.
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Enhanced Secure Digital Host Controller 11.6.4.1 Query, Enable and Disable SDIO High Speed Mode The following pseudo code shows enabling and disabling the high speed mode for SDIO using CMD52.
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Enhanced Secure Digital Host Controller 11.6.4.3 Query, Enable and Disable MMC High Speed Mode The following pseudo code shows enabling and disabling the high speed mode for MMC using CMD6.
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Enhanced Secure Digital Host Controller 11.6.5 Commands for MMC/SD/SDIO See Table 11-26 for the list of commands for the MMC/SD/SDIO cards. Refer to the corresponding specifications for details about the command information.
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Enhanced Secure Digital Host Controller Table 11-26. Commands for MMC/SD/SDIO (continued) CMD INDEX Type Argument Resp Description1 Abbreviation CMD7 ac [31–16] RCA [15–0] stuff bits R1b SELECT/DESELECT_CARD Command toggles a card between the stand-by and transfer states or between the programming and disconnect states. In both cases, the card is selected by its own relative address and gets deselected by any other address; address 0 deselects all.
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Enhanced Secure Digital Host Controller Table 11-26. Commands for MMC/SD/SDIO (continued) CMD INDEX Type Argument Resp Description1 Abbreviation CMD24 adtc [31–0] data address R1 WRITE_BLOCK Writes a block of the size selected by the SET_BLOCKLEN command. CMD25 adtc [31–0] data address R1 WRITE_MULTIPLE_BLOCK Continuously writes blocks of data until the STOP_TRANSMISSION command is received. CMD26 adtc [31–0] stuff bits R1 PROGRAM_CID Programming of the card identification register.
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Enhanced Secure Digital Host Controller Table 11-26. Commands for MMC/SD/SDIO (continued) CMD INDEX Type Argument Resp Description1 Abbreviation CMD38 ac [31–0] stuff bits R1b ERASE Erase all previously selected sectors. CMD39 ac [31–16] RCA [15] register write flag [14–8] register address [7–0] register data R4 FAST_IO Used to write and read 8-bit (register) data fields. The command address a card and a register and provides the data for writing if the write flag is set.
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Enhanced Secure Digital Host Controller Table 11-26. Commands for MMC/SD/SDIO (continued) CMD INDEX Type ACMD22 adtc ACMD23 Argument Resp Description1 Abbreviation [31–0] stuff bits R1 SEND_NUM_WR_ SECTORS Send the number of the written (without errors) sectors. Responds with 32 bit + CRC data block.
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Enhanced Secure Digital Host Controller 11.7 Software Restrictions This section discusses the software restrictions. 11.7.1 Initialization Active The driver should not set INITA bit in System Control register when any of the command line or data lines is active, so the driver should ensure both CDIHB and CIHB bits are cleared. In order to auto clear the INITA bit, the SDCLKEN bit must be ‘1’, otherwise no clocks can go out to the card and INITA never clears. 11.7.
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Enhanced Secure Digital Host Controller MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev.
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Chapter 12 DMA Controller (DMAC) The direct memory access (DMA) is a second-generation platform module capable of performing complex data transfers with minimal intervention from a host processor through 16 programmable channels. The hardware micro-architecture includes a DMA engine, which performs source and destination address calculations, and the actual data movement operations, along with a local memory containing the transfer control descriptors (TCD) for the channels.
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DMA Controller (DMAC) be transferred is statically known, and is not defined within the data packet itself. The DMA hardware supports: • 16 Channels • 32-byte transfer control descriptor per channel stored in local memory • 32 bytes of data registers, used as temporary storage to support burst transfers Throughout this section, n is used to reference the channel number. Additionally, data sizes are defined as byte (8-bit), half-word (16-bit), word (32-bit), and double word (64-bit). 12.1.
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DMA Controller (DMAC) to a reserved memory location results in a bus error. Reserved memory locations are indicated in the memory map. Table 12-1 is a 32-bit view of the DMA memory map. Table 12-1. DMAC Register Summary Offset Register Access Reset Section/Page R/W 0x0000_E400 12.2.1/12-3 Block Base Address: 0x2_C000 0x000 DMACR—DMA Control Register 0x004 DMAES—DMA Error Status Register R 0x0000_0000 12.
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DMA Controller (DMAC) = 0–15”). In round robin arbitration mode, the channel priorities are ignored and the channels within this group are cycled through without regard to priority. Minor loop offsets are address offset values added to the final source address (saddr) or destination address (daddr) upon minor loop completion.
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DMA Controller (DMAC) Table 12-2. DMA Control Register (DMACR) Field Descriptions (continued) Bits Name Description 16 ECX Error cancel transfer. 0 Normal operation. 1 Cancel the remaining data transfer in the same fashion as the CX cancel transfer. Stop the executing channel and force the minor loop to be finished. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel has been honored.
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DMA Controller (DMAC) 12.3 DMA Error Status (DMAES) The DMAES register provides information concerning the last recorded channel error. Channel errors can be caused by a configuration error (an illegal setting in the transfer control descriptor or an illegal priority register setting in fixed arbitration mode) or an error termination to a bus master read or write cycle.
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DMA Controller (DMAC) descriptor done flag and the possible assertion of an interrupt request, are not affected when an error is detected. See Table 12-3 for the DMAES definition. Figure 12-3 shows the DMA error status register. Offset 0x004 Access: Read Only 31 30 17 R VLD Reset All zeros 15 R W ECX — W 16 — 14 13 8 CPE ERRCHN[5:0] Reset 7 6 5 4 3 2 1 0 SAE SOE DAE DOE NCE SGE SBE DBE All zeros Figure 12-3. DMA Error Status Register (DMAES) Table 12-3.
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DMA Controller (DMAC) Table 12-3. DMAES Field Descriptions (continued) Bits Name 4 DOE Destination offset error. 0 No destination offset configuration error. 1 The last recorded error was a configuration error detected in the TCD.doff field. TCD.doff is inconsistent with TCD.dsize. 3 NCE Nbytes/citer configuration error. 0 No nbytes/citer configuration error. 1 The last recorded error was a configuration error detected in the TCD.nbytes or TCD.citer fields. TCD.nbytes is not a multiple of TCD.
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DMA Controller (DMAC) See Table 12-4 for the DMAEEI definition. Table 12-4. DMAEEI Field Descriptions Bits Name 31–16 — 15–0 EEIn 12.3.2 Description Reserved Enable error interrupt n. 0 The error signal for channel n does not generate an error interrupt. 1 The assertion of the error signal for channel n generate an error interrupt request.
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DMA Controller (DMAC) Offset 0x01B Access: Read/Write 7 R W 6 0 NOP CEEI[6–0] Reset All zeros Figure 12-6. DMA Clear Enable Error Interrupt Register Table 12-6 defines the DMACEEI fields. Table 12-6. DMACEEI Field Descriptions Bits Name 7 NOP No operation. 0 Normal operation. 1 No operation, ignore bits 6–0. 6–0 CEEI Clear enable error interrupt. 0–15 Clear corresponding bit in DMAEEI. 16–63 Reserved 64–127 Clear all bits in DMAEEI. 12.3.
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DMA Controller (DMAC) 12.3.5 DMA Clear Error (DMACERR) DMACEER, shown in Figure 12-8, provides a simple memory-mapped mechanism to clear a given bit in the DMAERR register to disable the error condition flag for a given channel. The given value on a register write causes the corresponding bit in DMAERR to be cleared.
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DMA Controller (DMAC) Table 12-9 defines DMASSRT fields. Table 12-9. DMASSRT Field Descriptions Bits Name 7 NOP No operation. 0 Normal operation. 1 No operation, ignore bits 6–0. 6–0 SSRT Set START bit (channel service request). 0–15 Set the corresponding channel’s TCD.start. 16–63 Reserved 64–127 Set all TCD.start bits. 12.3.
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DMA Controller (DMAC) interrupt controller. During the execution of the interrupt service routine associated with any given channel, it is software’s responsibility to clear the appropriate bit, negating the interrupt request. Typically, a write to the DMACINT register in the interrupt service routine is used for this purpose. The state of any given channel’s interrupt request is directly affected by writes to this register; it is also affected by writes to the DMACINT register.
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DMA Controller (DMAC) one in any bit position clears the corresponding channel’s error status; a zero in any bit position has no effect. DMACERR is provided so the error indicator for a single channel can easily be cleared.
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DMA Controller (DMAC) See Table 12-13 for the DMAGPOR definition. Table 12-13. DMAGPOR Field Descriptions Bits Name 31–13 — 12 DMA_PRIORITY 11–7 — 6 5 4 Description Reserved DMA priority. 0 Low priority 1 High priority Reserved SNOOP_ENABLE Snoop attribute. 0 DMA transactions are not snooped by e300 CPU data cache 1 DMA transactions are snooped by e300 CPU data cache — Reserved ERROR_DISABLE Ignore or react to bus errors.
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DMA Controller (DMAC) A channel’s ability to preempt another channel can be disabled by setting the DPA bit in the DCHPRI register. When a channel’s preempt ability is disabled, that channel cannot suspend a lower priority channel’s data transfer; regardless of the lower priority channel’s ECP setting. This allows for a pool of low priority, large data moving channels to be defined.
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DMA Controller (DMAC) 1, ..., channel [n – 1]. The definitions of the TCD are presented as eight 32-bit values. Table 12-15 is a 32-bit view of the basic TCD structure. Table 12-15.
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DMA Controller (DMAC) Figure 12-16 shows the TCD word 1 field. Offset DMA_Offset = 0x1000 + (32  n) + 0x04 31 27 R smod[4–0] W Access: Read/Write 26 24 23 ssize[2–0] Reset 19 dmod[4–0] 18 16 dsize[2–0] All zeros 15 0 R soff[15–0] W Reset All zeros Figure 12-16. TCD Word 1 (TCDn.{soff, smod, ssize, dmod, dsize}) Fields Table 12-17 describes the TCD word 1 fields. Table 12-17. TCD Word 1 (TCD.
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DMA Controller (DMAC) Offset DMA_Offset = 0x1000 + 0x08 31 R W 30 Access: Read/Write 29 smloe dmloe 10 9 nbytes[29:10] or mloff [19:0] Reset 0 nbytes[9:0] All zeros Figure 12-17. TCD Word 2 (TCD.{smloe, dmloe, nbytes}) Field Table 12-18 describes the TCD word 2 fields. Table 12-18. TCD Word 2 (TCD.{smloe, dmloe, nbytes}) Description Bits Name 31 smloe Source minor loop offset enable.
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DMA Controller (DMAC) Table 12-19 describes the TCD word 3 fields. Table 12-19. TCD Word 3 (TCD.slast) Field Descriptions Bits Name 31–0 slast Description Last source address adjustment. Adjustment value added to the source address at the completion of the outer major iteration count. This value can be applied to ‘restore’ the source address to the initial value, or adjust the address to reference the next data structure. Figure 12-19 shows the TCD word 4 field.
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DMA Controller (DMAC) Table 12-21 describes the TCD word 5 fields. Table 12-21. TCD Word 5 (TCD.{citer, doff} Field Descriptions Bits Name Description 31 citer.e_link Enable channel-to-channel linking on minor loop complete. As the channel completes the inner minor loop, this flag enables the linking to another channel, defined by citer.linkch[5:0]. The link target channel initiates a channel service request via an internal mechanism that sets the TCD.start bit of the specified channel.
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DMA Controller (DMAC) Table 12-22 describes the TCD word 6 fields. Table 12-22. TCD Word 6 (TCD.dlast_sga) Field Descriptions Bits 31–0 Name Description dlast_sga Last destination address adjustment or the memory address for the next transfer control descriptor to be [31–0] loaded into this channel (scatter/gather). If (TCD.e_sg = 0), then Adjustment value added to the destination address at the completion of the outer major iteration count.
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DMA Controller (DMAC) Table 12-23. TCD Word 7 (TCD.{biter, control/status}) Field Descriptions (continued) Bits Name Description 24–16 biter[8–0] Beginning major iteration count. This is the initial value copied into the citer field or citer.linkch field when the major loop is completed. The citer fields controls the iteration count and linking during channel execution. This 9 or 15-bit counter presents the beginning major loop count for the channel.
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DMA Controller (DMAC) Table 12-23. TCD Word 7 (TCD.{biter, control/status}) Field Descriptions (continued) Bits Name Description 2 int_half Enable an interrupt when major counter is half complete. If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the DMAINT register when the current major iteration count reaches the halfway point. Specifically, the comparison performed by the DMA engine is (citer == (biter >> 1)).
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DMA Controller (DMAC) • — data_path: This module implements the actual bus master read/write data path. It includes 32 bytes of register storage (matching the maximum transfer size) and the necessary mux logic to support any required data alignment. — pmodel_charb: This module implements the first section of DMA programming model as well as the channel arbitration logic. The programming model registers are connected to the register interface (not shown).
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DMA Controller (DMAC) minimize the time needed to fetch the activated channel’s descriptor and load it into the DMA engine addr_path.channel_{x,y} registers. addr wdata[31:0] 0 DMA AHB Interface SRAM Transfer Control Descriptor (TCD) n–1 DMA Engine Register Interface j j+1 pmodel_charb data_path addr_path control rdata[31:0] dma_ipi_int[n – 1:0] Figure 12-23.
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DMA Controller (DMAC) This source read/destination write processing continues until the inner minor byte count has been transferred. addr wdata[31:0] 0 DMA AHB Interface SRAM Transfer Control Descriptor (TCD) n–1 DMA Engine Register Interface j j+1 pmodel_charb data_path addr_path control rdata[31:0] dma_ipi_int[n – 1:0] Figure 12-24. DMA Operation—Part 2 Once the inner minor byte count has been moved, the final phase of the basic data flow is performed.
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DMA Controller (DMAC) descriptor. The updates to the TCD memory and the assertion of an interrupt request are shown in Figure 12-25. addr wdata[31:0] 0 DMA AHB Interface SRAM Transfer Control Descriptor (TCD) n–1 DMA Engine Register Interface j j+1 pmodel_charb data_path addr_path control rdata[31:0] dma_ipi_int[n – 1:0] Figure 12-25. DMA Operation—Part 3 12.5 Initialization/Application Information This section discusses the DMA initialization and programming errors. 12.5.
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DMA Controller (DMAC) channel into its internal address path module. As the TCD is being read, the first transfer is initiated on the AHB bus unless a configuration error is detected. Transfers from the source (as defined by the source address, TCD.saddr) to the destination (as defined by the destination address, TCD.daddr) continue until the specified number of bytes (TCD.nbytes) have been transferred. When the transfer is complete, the DMA engine's local TCD.saddr, TCD.daddr, and TCD.
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DMA Controller (DMAC) • • • • • • • = 0x2000 TCD.doff = 4 TCD.dsize = 2 TCD.dlast_sga= –16 TCD.int_maj = 1 TCD.start = 1 (TCD.word7 should be written last after all other fields have been initialized) All other TCD fields = 0 TCD.daddr This would generate the following sequence of events: 1. Register interface write to the TCD.start bit requests channel service. 2. Software sets the TCD.start bit of the channel for activation. The channel is selected by arbitration for servicing. 3.
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DMA Controller (DMAC) 2. DMA engine writes: TCD.done = 0, TCD.start = 0, TCD.active = 1. 3. DMA engine reads: channel TCD data from local memory to internal register file. 4.
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DMA Controller (DMAC) 12.7 TCD Status This section discusses the two methods to test for minor loop completion and explains active channel TCD reads. 12.7.1 Minor Loop Complete There are two methods to test for minor loop completion when using software initiated service requests. The first method is to read the TCD.citer field and test for a change. Another method may be extracted from the sequence shown below. The second method is to test the TCD.start bit AND the TCD.active bit.
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DMA Controller (DMAC) 12.8 Channel Linking Channel linking (or chaining) is a mechanism where one channel sets the TCD.start bit of another channel (or itself), and initiates a service request for that channel. This operation is automatically performed by the DMA engine at the conclusion of the major or minor loop when properly enabled. The minor loop channel linking occurs at the completion of the minor loop (or one iteration of the major loop). The TCD.citer.
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DMA Controller (DMAC) 12.9.2 Dynamic channel linking and dynamic scatter/gather Dynamic channel linking and dynamic scatter/gather is the process of changing the TCD.major.e_link or TCD.e_sg bits during channel execution. These bits are read from the TCD local memory at the end of channel execution. Therefore, allows the user to enable either feature during channel execution. Because the user is allowed to change the configuration during execution, a coherency model is needed.
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Chapter 13 Universal Serial Bus Interface This chapter describes the universal serial bus (USB) interface of the device. The USB interface implements many industry standards. However, it is beyond the scope of this document to document the intricacies of these standards. Instead, it is left to the reader to refer to the governing specifications. The following documents are available from the USB Implementers Forum web page at http://www.usb.org/developers/docs/. • Universal Serial Bus Revision 2.
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Universal Serial Bus Interface 13.1.1 Overview The USB DR module is a USB 2.0-compliant serial interface engine for implementing a USB interface. The registers and data structures for the module are based on the Enhanced Host Controller Interface Specification for Universal Serial Bus (EHCI) from Intel Corporation. The DR module can act as a device or host controller.
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Universal Serial Bus Interface 13.2 External Signals This section contains detailed descriptions of all the USB dual-role controller signals. Many of the signals for the PHY interfaces are muxed onto the same pins in order to reduce pin count. Table 13-1 describes the signals, indicating which interface supports each signal. Table 13-1. USB External Signals 13.2.
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Universal Serial Bus Interface Table 13-2. ULPI Signal Descriptions (continued) Signal I/O USBDR_STP Description O Stop. USBDR_STP indicates the end of a transfer on the bus. State Asserted—USB asserts this signal for 1 clock cycle to stop the data stream Meaning currently on the bus. If USB port is sending data to the PHY, USBDR_STP indicates the last byte of data was previously on the bus.
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Universal Serial Bus Interface Table 13-3. USB Interface Memory Map (continued) Offset 0x100 Register CAPLENGTH—Capability register length number1 Access Reset Section/Page R 0x40 13.3.1.1/13-6 R 0x0100 13.3.1.2/13-7 0x102 HCIVERSION—Host interface version 0x104 HCSPARAMS—Host controller structural parameters1 R 0x0001_0011 13.3.1.3/13-7 0x108 HCCPARAMS—Host controller capability parameters1 R 0x0000_0006 13.3.1.
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Universal Serial Bus Interface Table 13-3. USB Interface Memory Map (continued) Offset 1 Register Access Reset Section/Page 0x40C PRI_CTRL—Priority control R/W 0x0000_0000 13.3.2.26/13-42 0x410 SI_CTRL—System interface control R/W 0x0000_0000 13.3.2.27/13-42 0x500 CONTROL—Control R/W 0x0000_0000 13.3.2.28/13-43 0x504– 0xFFF Reserved, should be cleared — — — This register has separate functions for the host and device operation; the host function is listed first in the table.
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Universal Serial Bus Interface Table 13-4 provides bit descriptions for the CAPLENGTH register. Table 13-4. CAPLENGTH Register Field Descriptions Bits Name 7–0 Description CAPLENGTH Capability registers length. Value is 0x40. 13.3.1.2 Host Controller Interface Version (HCIVERSION) HCIVERSION contains a BCD encoding of the EHCI revision number supported by this host controller. The most-significant byte of the register represents a major revision and the least-significant byte is the minor revision.
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Universal Serial Bus Interface Table 13-6. HCSPARAMS Register Field Descriptions (continued) Bits Name 23–20 N_PTT 19–17 — Reserved, should be cleared. 16 PI Port indicators. Indicates whether the ports support port indicator control. Always 1. 1 The port status and control registers include a R/W field for controlling the state of the port indicator. 15–12 N_CC 11–8 N_PCC 7–5 — 4 PPC 3–0 N_PORTS 13.3.1.4 Description Ports per transaction translator. This is a non-EHCI field.
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Universal Serial Bus Interface Table 13-7. HCCPARAMS Register Field Descriptions (continued) Bits Name Description 2 ASP Asynchronous schedule park capability. Indicates whether the USB DR module supports the park feature for high-speed queue heads in the asynchronous schedule. The feature can be disabled or enabled and set to a specific level using the asynchronous schedule park mode enable and asynchronous schedule park mode count fields in the USBCMD register.
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Universal Serial Bus Interface 13.3.1.6 Device Controller Capability Parameters (DCCPARAMS)—Non-EHCI This register is not defined in the EHCI specification. This register describes the overall host/device capability of the DR module. Figure 13-7 shows the DCCPARAMS register. Offset 0x124 Access: Read-only 31 9 R 7 6 HC DC — W 8 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 5 4 0 DEN — 0 0 0 0 0 1 1 Figure 13-7.
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Universal Serial Bus Interface Table 13-10 provides bit descriptions for the USBCMD register. Table 13-10. USBCMD Register Field Descriptions Bits Name Description 31–24 — 23–16 ITC Interrupt threshold control. The system software uses this field to set the maximum rate at which the USB DR module issues interrupts. ITC contains the maximum interrupt interval measured in microframes. Valid values are shown below.
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Universal Serial Bus Interface Table 13-10. USBCMD Register Field Descriptions (continued) Bits Name Description 5 ASE Asynchronous schedule enable. Controls whether the controller skips processing the asynchronous schedule. Only used in host mode. 0 Do not process the asynchronous schedule 1 Use the ASYNCLISTADDR register to access the asynchronous schedule. 4 PSE Periodic schedule enable. Controls whether the controller skips processing the periodic schedule. Only used in host mode.
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Universal Serial Bus Interface 13.3.2.2 USB Status Register (USBSTS) Figure 13-9 shows the USB status register, which indicates various states of the USB DR module and any pending interrupts. This register does not indicate status resulting from a transaction on the serial bus. Software clears certain bits in this register by writing a 1 to them (indicated by a w1c in the bit’s W cell).
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Universal Serial Bus Interface Table 13-11. USBSTS Register Field Descriptions (continued) Bits Name Description 8 SLI DCSuspend. This is a non-EHCI bit. When a device controller enters a suspend state from an active state, this bit is set. The device controller clears the bit upon exiting from a suspend state. Only used by the device controller. 0 Active 1 Suspended 7 SRI Host mode: • This is a non-EHCI status bit.
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Universal Serial Bus Interface Table 13-11. USBSTS Register Field Descriptions (continued) Bits 1 Name Description UEI USB error interrupt (USBERRINT). When completion of a USB transaction results in an error (USBERRINT) condition, this bit is set by the controller. This bit is set along with the UI, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. See Section 4.15.1 in EHCI for a complete list of host error interrupt conditions.
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Universal Serial Bus Interface Table 13-12. USBINTR Register Field Descriptions (continued) Bits Name 8 SLE Sleep enable. This is a non-EHCI bit. When this bit is a one, and USBSTS[SLI] transitions, the USB DR controller issues an interrupt. The interrupt is acknowledged by software writing a one to USBSTS[SLI]. Only used in device mode. 0 Disable 1 Enable 7 SRE SOF received enable. This is a non-EHCI bit. When this bit is a one, and USBSTS[SRI] is a one, the controller issues an interrupt.
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Universal Serial Bus Interface This register must be written as a DWord. Byte writes produce-undefined results. This register cannot be written unless the USB DR controller is in the Halted state as indicated by the USBSTS[HCH]. A write to this register while USBCMD[RS] is set produces undefined results. Writes to this register also affect the SOF value. In device mode, this register is read-only and the USB DR controller updates the FRINDEX[13–3] register from the frame number indicated by the SOF marker.
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Universal Serial Bus Interface Table 13-14. FRINDEX N Values (continued) 13.3.2.5 USBCMD[FS] Frame List Size FRINDEX N value 110 16 elements (64 bytes) 6 111 8 elements (32 bytes) 5 Control Data Structure Segment Register (CTRLDSSEGMENT) The CTRLDSSEGMENT register is not implemented on MPC8308. 13.3.2.6 Periodic Frame List Base Address Register (PERIODICLISTBASE) This register contains the beginning address of the Periodic Frame List in the system memory.
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Universal Serial Bus Interface Note that this register is shared between the host and device mode functions. In device mode, it is the DEVICEADDR register; in host mode, it is the PERIODICLISTBASE register. See Section 13.3.2.6, “Periodic Frame List Base Address Register (PERIODICLISTBASE),” for more information. Figure 13-12 shows the device address register. Offset 0x154 Access: Read/Write 31 25 24 R 0 USBADR W — Reset All zeros Figure 13-13.
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Universal Serial Bus Interface Table 13-17 describes the current asynchronous list address register. Table 13-17. ASYNCLISTADDR Register Field Descriptions Bits Name 31–5 ASYBASE 4–0 — 13.3.2.9 Description Link pointer low (LPL). These bits correspond to memory address signals [31:5]. This field may only reference a queue head (QH). Only used by the host controller. Reserved, should be cleared.
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Universal Serial Bus Interface Offset 0x160 Access: Read/Write 31 16 15 R — W Reset 0 8 0 0 0 0 0 0 0 7 0 TXPBURST 0 0 0 0 0 0 0 0 0 0 0 1 0 0 RXPBURST 0 0 0 0 0 1 0 0 0 0 Figure 13-16. Master Interface Data Burst Size (BURSTSIZE) Table 13-19 describes the master interface data burst size register fields. Table 13-19. BURSTSIZE Register Field Descriptions Bits Name 31–16 — Description Reserved, should be cleared. 15–8 TXPBURST Programmable TX burst length.
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Universal Serial Bus Interface bandwidth and power on the system bus and thus should be minimized (not necessarily eliminated). Back-offs can be minimized with use of the TSCHHEALTH (Tff) parameter described below. Offset 0x164 Access: Read/Write 31 22 21 R — W Reset 0 0 0 0 0 16 15 TXFIFOTHRES 0 0 0 0 0 0 0 0 0 0 13 12 — 0 0 0 8 7 0 TXSCHHEALTH 0 0 0 0 0 0 TXSCHOH 0 0 0 0 0 0 0 0 Figure 13-17.
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Universal Serial Bus Interface 13.3.2.12 ULPI Register Access (ULPI VIEWPORT) The ULPI register access provides indirect access to the ULPI PHY register set. Although the controller modules perform access to the ULPI PHY register set, there may be extraordinary circumstances where software may need direct access. Be advised that writes to the ULPI through the ULPI viewport can substantially harm standard USB operations.
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Universal Serial Bus Interface Table 13-21. ULPI VIEWPORT Field Descriptions (continued) Bits Name Description 23–16 ULPIADDR When a read or write operation is commanded, the address of the operation is written to this field. 15–8 ULPIDATRD After a read operation completes, the result is placed in this field. 7–0 ULPIDTWR When a write operation is commanded, the data to be sent is written to this field.
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Universal Serial Bus Interface Table 13-22 describes the configure flag register fields. Table 13-22. CONFIGFLAG Register Field Descriptions Bits Name Description 31–1 — Reserved. 0 CF Configure flag. Always 1 indicating all port routings default to this host. 13.3.2.14 Port Status and Control Register (PORTSC) The port status and control (PORTSC) register, shown in Figure 13-20, is only reset when power is initially applied or in response to a controller reset.
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Universal Serial Bus Interface Table 13-23. PORTSC Register Field Descriptions (continued) Bits Name Description 27–26 PSPD Port speed. This read-only register field indicates the speed at which the port is operating. This bit is not defined in the EHCI specification. 00 Full-speed 01 Low-speed 10 High-speed 11 Undefined 25 — Reserved, should be cleared 24 PFSC Port force full-speed connect. Used to disable the chirp sequence that allows the port to identify itself as a HS port.
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Universal Serial Bus Interface Table 13-23. PORTSC Register Field Descriptions (continued) Bits Name Description 15–14 PIC Port indicator control. Control the link indicator signals. These signals are valid for host mode only. 00 Off 01 Amber 10 Green 11 Undefined Refer to the USB Specification Revision 2.0 [3] for a description on how these bits are to be used. This field is output from the module on the USB port control signals for use by an external LED driving circuit. 13 PO Port owner.
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Universal Serial Bus Interface Table 13-23. PORTSC Register Field Descriptions (continued) Bits 7 Name Description SUSP Suspend. Host mode: • The port enabled bit (PE) and suspend (SUSP) bit define the port states as follows: 0x Disable 10 Enable 11 Suspend • When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1.
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Universal Serial Bus Interface Table 13-23. PORTSC Register Field Descriptions (continued) Bits Name Description 4 OCA Over-current active. This bit will automatically transition from one to zero when the over current condition is removed. Host/OTG mode: • The user can provide over-current detection to the USBn_PWRFAULT signal for this condition. Device mode: • This bit must always be 0. 1 Port currently in over-current condition. 0 Port not in over-current condition.
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Universal Serial Bus Interface 13.3.2.15 On-The-Go Status and Control (OTGSC)—Non-EHCI This register is not defined in the EHCI specification. The USB DR module implements one On-The-Go (OTG) status and control register corresponding to Port 0. The OTGSC register has four sections: • OTG interrupt enables (Read/Write) • OTG interrupt status (Read/Write to Clear) • OTG status inputs (Read Only) • OTG controls (Read/Write) The status inputs are de-bounced using a 1-msec time constant.
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Universal Serial Bus Interface Table 13-24. OTGSC Register Field Descriptions (continued) Bits Name Description 25 AVVIE 24 IDIE 23 — 22 DPIS Data pulse interrupt status. Set when data bus pulsing occurs on DP or DM. Data bus pulsing is only detected when USBMODE[CM] = Host (11) and PORTSC[PP] (port power) = Off (0). Software must write a one to clear this bit. 21 1msS 1-millisecond timer interrupt status. Set once every millisecond. Software must write a one to clear this bit.
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Universal Serial Bus Interface Table 13-24. OTGSC Register Field Descriptions (continued) Bits Name Description 8 ID USB ID 1 B device 0 A device 7–5 — Reserved, should be cleared. 4 DP Data pulsing 1 The pullup on DP is asserted for data pulsing during SRP. 0 The pullup on DP is not asserted. 3 OT OTG termination. This bit must be set when the OTG device is in device mode. 1 Enable pulldown on DM 0 Disable pulldown on DM 2 — Reserved, should be cleared. 1 VC VBUS charge.
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Universal Serial Bus Interface Table 13-25 describes the USB mode register fields. Table 13-25. USBMODE Register Field Descriptions Bits Name Description 31–5 — 4 SDIS 3 SLOM Setup lockout mode. In device mode, this bit controls behavior of the setup lock mechanism. See Section 13.8.3.5, “Control Endpoint Operation Model.” 1 Setup lockouts off. DCD requires use of setup data buffer tripwire in USBCMD (SUTW). 0 Setup lockouts on Reserved, should be cleared.
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Universal Serial Bus Interface Table 13-26 describes the endpoint setup status register fields. Table 13-26. ENDPTSETUPSTAT Register Field Descriptions Bits Name 31–3 — 2–0 Description Reserved, should be cleared. ENDPTSETUP Setup endpoint status. For every setup transaction that is received, a corresponding bit in this STAT register is set. Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from queue head.
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Universal Serial Bus Interface 13.3.2.19 Endpoint Flush Register (ENDPTFLUSH)—Non-EHCI The endpoint flush register, shown in Figure 13-25, is not defined in the EHCI specification. This register is only used in device mode. Offset 0x1B4 Access: Read/Write 31 19 18 R — W 16 15 FETB Reset 3 2 — 0 FERB All zeros Figure 13-25. Endpoint Flush (ENDPTFLUSH) Table 13-28 describes the endpoint flush register fields. Table 13-28.
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Universal Serial Bus Interface Table 13-29 describes the endpoint status fields. Table 13-29. ENDPTSTATUS Register Field Descriptions Bits Name 31–19 — Description Reserved, should be cleared 18–16 ETBR Endpoint transmit buffer ready. One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register.
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Universal Serial Bus Interface Table 13-30. ENDPTCOMPLETE Register Field Descriptions (continued) Bits Name 15–3 — 2–0 Description Reserved, should be cleared ERCE Endpoint receive complete event. Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT.
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Universal Serial Bus Interface Table 13-31. ENDPTCTRL0 Register Field Descriptions (continued) Bits Name 1 — 0 RXS Description Reserved, should be cleared. RX endpoint stall Software can write a one to this bit to force the endpoint to return a STALL handshake to the host. It will continue returning STALL until the bit is cleared by software or it will automatically be cleared upon receipt of a new SETUP request. 1 Endpoint stalled 0 Endpoint OK 13.3.2.
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Universal Serial Bus Interface Table 13-32. ENDPTCTRLn Register Field Descriptions (continued) Bits Name Description 16 TXS TX endpoint stall. This bit is set automatically upon receipt of a SETUP request if this endpoint is not configured as a control endpoint. It is cleared automatically upon receipt of a SETUP request if this endpoint is configured as a control endpoint. Software can write a one to this bit to force the endpoint to return a STALL handshake to the host.
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Universal Serial Bus Interface as shown below. This provides a snooping region of 4 Kbytes to 2 Gbytes within each starting base address that is programmed by the core. The SNOOPn[20–26] are not used. Offset 0x400 (SNOOP1), 0x404 (SNOOP2) Access: Read/Write 0 19 20 R Snoop Address W Reset 26 27 — 31 Snoop Enables All zeros Figure 13-30. Snoop 1 and Snoop 2 (SNOOPn) Table 13-33 describes the SNOOPn register fields. Table 13-33.
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Universal Serial Bus Interface If the aging counter is less than the AGE_CNT_THRESH value, priority state zero is chosen. If the aging counter is greater than or equal to the AGE_CNT_THRESH value, priority state one is chosen. The aging counter begins to count from zero when a bus access is requested. It increments every bus cycle until the bus transaction completes. At the completion of a bus transaction, the counter is synchronously reset to zero.
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Universal Serial Bus Interface increments of 5. Raising AGE_CNT_THRESH benefits the other controllers on the system bus by reducing the frequency that this USB controller raises its priority to the arbiter. 13.3.2.26 Priority Control Register (PRI_CTRL)—Non-EHCI Note that this register uses big-endian byte ordering and is not defined in the EHCI specification. The priority control (PRI_CTRL) register sets the priority level for each of two priority states.
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Universal Serial Bus Interface Table 13-36 describes the system interface control register fields. Table 13-36. SI_CTRL Register Field Descriptions Bits Name 0–26 — 27 err_disable 28–30 — 31 Description Reserved, should be cleared When this bit is set, it causes the controller to ignore system bus errors. If cleared the controller responds according to the values set in USBSTS[SEI] and USBINT[SEE].
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Universal Serial Bus Interface Table 13-37. CONTROL Field Descriptions (continued) Bits Name Description 15 WU_INT Reflects the state of the wake up interrupt. The wake up interrupt signal is asserted when a wake-up event occurs while in a low-power suspend state. If WU_INT_EN is set, this WU_INT signal generates an interrupt to the system to indicate wake up servicing is required. WU_INT will remain set until the USB controller is exited from the low power by clearing the PORTSC[PHCD] bit.
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Universal Serial Bus Interface 13.4.2 DMA Engine The module contains a local DMA engine. The DMA engine interfaces internally to the CSB. It is responsible for moving all of the data to be transferred over the USB between the module and buffers in system memory. Like the system interface block, the DMA engine block uses a simple synchronous bus signaling protocol that eases connections to a number of different standard buses.
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Universal Serial Bus Interface section support a 32-bit memory buffer address space. The interface consists of a periodic schedule, periodic frame list, asynchronous schedule, isochronous transaction descriptors, split-transaction isochronous transfer descriptors, queue heads, and queue element transfer descriptors. The periodic frame list is the root of all periodic (isochronous and interrupt transfer type) support for the host controller interface.
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Universal Serial Bus Interface The periodic frame list is a 4K-page aligned array of frame list link pointers. The length of the frame list may be programmable. The programmability of the periodic frame list is exported to system software through the HCCPARAMS register. If non-programmable, the length is 1024 elements. If programmable, the length can be selected by system software as one of 256, 512, or 1024 elements. An implementation must support all three sizes.
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Universal Serial Bus Interface Operational Registers Bulk/Control Queue Heads AsyncListAddr H Figure 13-37. Asynchronous Schedule Organization The asynchronous list is a simple circular list of queue heads. The ASYNCLISTADDR register is simply a pointer to the next queue head. This implements a pure round-robin service for all queue heads linked into the asynchronous list. 13.5.
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Universal Serial Bus Interface 2 These fields may be modified by the host controller if the I/O field indicates an OUT. 13.5.3.1 Next Link Pointer The first DWord of an iTD is a pointer to the next schedule data structure, as shown in Table 13-40. Table 13-40. Next Schedule Element Pointer Bits 31–5 Name Description Link Pointer Correspond to memory address signals [31:5], respectively. This field points to another isochronous transaction descriptor (iTD/siTD) or queue head (QH).
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Universal Serial Bus Interface Table 13-41 shows the iTD transaction status and control fields. Table 13-41. iTD Transaction Status and Control Bits Name Description 31–28 Status Records the status of the transaction executed by the host controller for this slot. This field is a bit vector with the following encoding: 31 Active. Set by software to enable the execution of an isochronous transaction by the host controller.
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Universal Serial Bus Interface Table 13-42–Table 13-45 describes buffer pointer page n. Table 13-42. Buffer Pointer Page 0 (Plus) Bits 31–12 Name Description Buffer Pointer (Page 0) A 4K-aligned pointer to physical memory. Corresponds to memory address bits 31–12. 11–8 EndPt Selects the particular endpoint number on the device serving as the data source or sink. 7 — 6–0 Device Address Reserved, should be cleared. Reserved for future use and should be initialized by software to zero.
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Universal Serial Bus Interface 13.5.4 Split Transaction Isochronous Transfer Descriptor (siTD) All full-speed isochronous transfers through the internal transaction translator are managed using the siTD data structure. This data structure satisfies the operational requirements for managing the split transaction protocol. Figure 13-39 shows the split-transaction isochronous transfer descriptor (siTD).
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Universal Serial Bus Interface Table 13-47 describes the endpoint and transaction translator characteristics. Table 13-47. Endpoint and Transaction Translator Characteristics Bits Name 31 I/O 30–24 Port Number This field is the port number of the recipient transaction translator. 23 — Reserved, should be cleared. Bit reserved and should be cleared. 22–16 Hub Address This field holds the device address of the companion controllers’ hub. 15–12 — Reserved, should be cleared.
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Universal Serial Bus Interface 13.5.4.3 siTD Transfer State DWords 3–6 manage the state of the transfer, as described in Table 13-49. Table 13-49. siTD Transfer Status and Control Bits Name Description 31 ioc 30 P Page select.
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Universal Serial Bus Interface 13.5.4.4 siTD Buffer Pointer List (Plus) DWords 4 and 5 are the data buffer page pointers for the transfer. This structure supports one physical page cross. The most-significant 20 bits of each DWord in this section are the 4K (page) aligned buffer pointers. The least-significant 12 bits of each DWord are used as additional transfer state. Table 13-50 describes the siTD buffer pointer page 0. Table 13-50.
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Universal Serial Bus Interface Table 13-52. siTD Back Link Pointer (continued) Bits Name 4–1 — Reserved, should be cleared. This field is reserved for future use. It should be cleared. 0 T Terminate 0 siTD Back Pointer field is valid 1 siTD Back Pointer field is not valid 13.5.5 Description Queue Element Transfer Descriptor (qTD) This data structure is only used with a queue head. This data structure is used for one or more USB transactions.
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Universal Serial Bus Interface 13.5.5.1 Next qTD Pointer The first DWord of an element transfer descriptor is a pointer to another transfer element descriptor. Table 13-53 describes the qTD next element transfer pointer. Table 13-53. qTD Next Element Transfer Pointer (DWord 0) Bits Name 31–5 Next qTD Pointer 4–1 — Reserved, should be cleared. These bits are reserved and their value has no effect on operation. 0 T Terminate.
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Universal Serial Bus Interface specified in the queue head). Note that some of the field descriptions in Table 13-55 reference fields are defined in the queue head. See Section 13.5.6, “Queue Head,” for more information on these fields. Table 13-55. qTD Token (DWord 2) Bits Name Description 31 dt Data toggle. This is the data toggle sequence bit. The use of this bit depends on the setting of the Data Toggle Control bit in the queue head. 30–16 Total Bytes to Transfer Total bytes to transfer.
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Universal Serial Bus Interface Table 13-55. qTD Token (DWord 2) (continued) Bits Name Description 11–10 Cerr Error counter. 2-bit down counter that keeps track of the number of consecutive errors detected while executing this qTD. If this field is programmed with a non-zero value during setup, the host controller decrements the count and writes it back to the qTD if the transaction fails.
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Universal Serial Bus Interface Table 13-55. qTD Token (DWord 2) (continued) Bits Name Description 7–0 Status This field is used by the host controller to communicate individual command execution states back to the host controller driver (HCD) software. This field contains the status of the last transaction performed on this qTD. The bit encodings are: Bits Status Field Description 7 Active. Set by software to enable the execution of transactions by the host controller. 6 Halted.
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Universal Serial Bus Interface Table 13-55. qTD Token (DWord 2) (continued) Bits Name 13.5.5.4 Description 1 Split transaction state (SplitXstate). This bit is ignored by the host controller unless the QH[EPS] field indicates a full- or low-speed endpoint. When a fullor low-speed device, the host controller uses this bit to track the state of the split- transaction.
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Universal Serial Bus Interface 13.5.6 Queue Head Figure 13-41 shows the queue head structure.
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Universal Serial Bus Interface Table 13-57. Queue Head DWord 0 (continued) Bits Name Description 2–1 Typ Indicates to the hardware whether the item referenced by the link pointer is an iTD, siTD or a QH. This allows the host controller to perform the proper type of processing on the item after it is fetched. 00 iTD (isochronous transfer descriptor) 01 QH (queue head) 10 siTD (split transaction isochronous transfer descriptor) 11 FSTN (frame span traversal node) 0 T Terminate.
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Universal Serial Bus Interface Table 13-58. Endpoint Characteristics: Queue Head DWord 1 (continued) Bits Name Description 14 dtc Data toggle control (DTC). Specifies where the host controller should get the initial data toggle on an overlay transition. 0 Ignore DT bit from incoming qTD. Host controller preserves DT bit in the queue head. 1 Initial data toggle comes from incoming qTD DT bit. Host controller replaces DT bit in the queue head from the DT bit in the qTD.
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Universal Serial Bus Interface Table 13-59. Endpoint Capabilities: Queue Head DWord 2 (continued) Bits Name Description 15–8 µFrame C-mask This field is ignored by the host controller unless the EPS field indicates this device is a low- or full-speed device and this queue head is in the periodic list. This field (along with the Active and SplitX-state fields) is used to determine during which microframes the host controller should execute a complete-split transaction.
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Universal Serial Bus Interface This area is characterized as an overlay because when the queue is advanced to the next queue element, the source queue element is merged onto this area. This area serves an execution cache for the transfer. Table 13-61 describes the host-controller rules for bits in overlay. Table 13-61. Host-Controller Rules for Bits in Overlay (DWords 5, 6, 8, and 9) DWord QH Offset Bits Name Description 5 0x14 4–1 NakCnt Nak counter—RW.
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Universal Serial Bus Interface 13.5.7.1 FTSN Normal Path Pointer The first DWord of an FSTN contains a link pointer to the next schedule object. This object can be of any valid periodic schedule data type. Table 13-62 describes the FTSN normal path pointer. Table 13-62. FTSN Normal Path Pointer Bits Name Description 31–5 NPLP Normal path link pointer. Contains the address of the next data object to be processed in the periodic list and corresponds to memory address signals [31:5], respectively.
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Universal Serial Bus Interface 13.6 Host Operations The general operational model for the USB DR module in host mode is defined by the EHCI specification. The EHCI specification describes the register-level interface for a host controller for the USB Revision 2.0. It includes a description of the hardware/software interface between system software and host controller hardware.
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Universal Serial Bus Interface schedules have not yet been enabled. The EHCI host controller will not transmit SOFs to enabled Full- or Low-speed ports. In order to communicate with devices via the asynchronous schedule, system software must write the ASYNDLISTADDR register with the address of a control or bulk queue head. Software must then enable the asynchronous schedule by writing a one to USBCMD[ASE].
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Universal Serial Bus Interface individual ports. The mechanisms allow the individual ports to be resumed completely through software initiation. Other control mechanisms are provided to parameterize the host controller's response (or sensitivity) to external resume events. In this discussion, host-initiated, or software-initiated resumes are called Resume Events/Actions; bus-initiated resume events are called wake-up events.
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Universal Serial Bus Interface System software observes the resume event on the port, delays a port resume time (nominally 20 milliseconds), then terminates the resume sequence by clearing PORTSC[FPR] in the port. The host controller receives the write of zero to PORTSC[FPR], terminates the resume sequence and clears PORTSC[FPR] and PORTSC[SUSP]. Software can determine that the port is enabled (not suspended) by sampling the PORTSC register and observing that the SUSP and FPR bits are zero.
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Universal Serial Bus Interface 13.6.5 Schedule Traversal Rules The host controller executes transactions for devices using a simple, shared-memory schedule. The schedule is comprised of a few data structures, organized into two distinct lists. The data structures are designed to provide the maximum flexibility required by USB, minimize memory traffic and hardware/software complexity. System software maintains two schedules for the host controller: a periodic schedule and an asynchronous schedule.
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Universal Serial Bus Interface Operational Registers USBCMD USBSTS H • • • AsyncListAddr • • • Figure 13-44. General Format of Asynchronous Schedule List The ASYNCLISTADDR register contains a physical memory pointer to the next queue head. When the host controller makes a transition to executing the asynchronous schedule, it begins by reading the queue head referenced by the ASYNCLISTADDR register.
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Universal Serial Bus Interface values are separate, but tightly coupled. The periodic frame list is accessed via the Frame List Index Register (FRINDEX). Bits FRINDEX[2–0], represent the microframe number. The SOF value is coupled to the value of FRINDEX[13–3]. Both FRINDEX[13–3] and the SOF value are incremented based on FRINDEX[2–0]. It is required that the SOF value be delayed from the FRINDEX value by one microframe.
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Universal Serial Bus Interface Software is allowed to write to FRINDEX. Section 13.3.2.4, “Frame Index Register (FRINDEX),” provides the requirements that software should adhere when writing a new value in FRINDEX. Table 13-65.
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Universal Serial Bus Interface linked first (for example, closest to the periodic frame list), followed by shorter poll rates, with queue heads with a poll rate of one, on the very end. Periodic Frame List • • • • • • Isochronous Transfer Descriptor(s) A Last Periodic has End of List Mark A A 1024, 512, or 256 Elements A A • • • A 4 A Poll Rate: 1 1 8 Poll Rate: N ––> 1 Interrupt Queue Heads Figure 13-47. Example Periodic Schedule 13.6.
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Universal Serial Bus Interface 13.6.8.1 Host Controller Operational Model for iTDs The host controller uses FRINDEX register bits 12–3 to index into the periodic frame list. This means that the host controller visits each frame list element eight consecutive times before incrementing to the next periodic frame list element. Each iTD contains eight transaction descriptions, which map directly to FRINDEX register bits 2–0. Each iTD can span 8 microframes worth of transactions.
PAGE 656
Universal Serial Bus Interface updates the appropriate record in the iTD and moves to the next schedule data structure. The maximum sized transaction supported is 3 ¥ 1024 bytes. For IN transfers, the host controller issues Mult transactions. It is assumed that software has properly initialized the iTD to accommodate all possible data. During each IN transaction, the host controller must use Maximum Packet Size to detect packet babble errors.
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Universal Serial Bus Interface Figure 13-48 illustrates the simple model of how a client buffer is mapped by system software to the periodic schedule (that is, the periodic frame list and a set of iTDs). Client Buffer • • • Client Request iTD0 USB Transaction Information Frame List Frame i Frame i+1 iTD1 • • • • • • Frame i+2 • • • • • • Frame i+n iTDN • • • Figure 13-48. Example Association of iTDs to Client Request Buffer On the right is the client description of its request.
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Universal Serial Bus Interface a page boundary. Doing so yields undefined behavior. The host controller hardware is not required to alias the page selector to page zero. USB 2.0 isochronous endpoints can specify a period greater than one. Software can achieve the appropriate scheduling by linking iTDs into the appropriate frames (relative to the frame list) and by setting appropriate transaction description elements active bits to a one. 13.6.8.2.
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Universal Serial Bus Interface state (current microframe, plus the next) on chip. On each microframe boundary, the host controller releases the current microframe state and begins accumulating the next microframe state. 13.6.9 Asynchronous Schedule The asynchronous schedule traversal is enabled or disabled through USBCMD[ASE] (asynchronous schedule enable). If USBCMD[ASE] is cleared, then the host controller simply does not try to access the asynchronous schedule via the ASYNCLISTADDR register.
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Universal Serial Bus Interface The maximum packet size field in a queue head is sized to accommodate the use of this data structure for all non-isochronous transfer types. The USB Specification, Revision 2.0 specifies the maximum packet sizes for all transfer types and transfer speeds. System software should always parameterize the queue head data structures according to the core specification requirements. 13.6.9.1 Adding Queue Heads to Asynchronous Schedule This is a software requirement section.
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Universal Serial Bus Interface -- pQHeadPrevious is a pointer to a queue head that -- references the queue head to remove -- pQHeadToUnlink is a pointer to the queue head to be -- removed -- pQheadNext is a pointer to a queue head still in the -- schedule. Software provides this pointer with the -- following strict rules: -- if the host software is one queue head, then -- pQHeadNext must be the same as -- QueueheadToUnlink.HorizontalPointer.
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Universal Serial Bus Interface When the host controller observes that doorbell bit being set, it makes a note of the local reachable schedule information. In this example, the local reachable schedule information includes both queue heads (A & B). It is sufficient that the host controller can set the status bit (and clear the doorbell bit) as soon as it has traversed beyond current reachable schedule information (that is, traversed beyond queue head (B) in this example).
PAGE 663
Universal Serial Bus Interface Figure 13-50 shows an example illustrating the H-bit in a schedule. Operational Registers USBCMD Reclamation Flag USBSTS • • • 1: Transaction Executed 0: Head of List Seen Typ T AsyncListAddr • • • Horizontal Ptr 1 H 01 0 Operational Area Typ T Horizontal Ptr 0 H 01 0 Operational Area Typ T Horizontal Ptr 0 H 01 0 Operational Area List Head Asynchronous Schedule Figure 13-50. Asynchronous Schedule List with Annotation to Mark Head of List 13.6.9.
PAGE 664
Universal Serial Bus Interface Queue heads use the Queue Element Transfer Descriptor (qTD) structure defined in Section 13.5.5, “Queue Element Transfer Descriptor (qTD).” One queue head is used to manage the data stream for one endpoint. The queue head structure contains static endpoint characteristics and capabilities. It also contains a working area from where individual bus transactions for an endpoint are executed.
PAGE 665
Universal Serial Bus Interface Figure 13-51 illustrates these requirements. 2047 The physical pages in memory may or may not be physically contiguous. C_Page = 0 Pointer (Page 0) 4096 Pointer (Page 1) Pointer (Page 2) 4096 Pointer (Page 3) Pointer (Page 4) 4096 Bytes to Transfer = 16383 bytes Page 0 Page 1 Page 2 Page 3 Page 4 Total: = = = = = 2047 4096 4096 4096 2048 16383 2048 Figure 13-51.
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Universal Serial Bus Interface host controller automatically moving to the next page pointer (that is, C_Page) when necessary. There are three conditions for how the host controller handles C_Page. • The current transaction does not span a page boundary. The value of C_Page is not adjusted by the host controller. • The current transaction does span a page boundary. The host controller must detect the page cross condition and advance to the next buffer while streaming data to/from the USB.
PAGE 667
Universal Serial Bus Interface 13.6.11 Ping Control USB 2.0 defines an addition to the protocol for high-speed devices called Ping. Ping is required for all USB 2.0 High-speed bulk and control endpoints. Ping is not allowed for a split-transaction stream. This extension to the protocol eliminates the bad side-effects of Naking OUT endpoints.
PAGE 668
Universal Serial Bus Interface 13.6.12 Split Transactions USB 2.0 defines extensions to the bus protocol for managing USB 1.x data streams through USB 2.0 hubs. This section describes how the host controller uses the interface data structures to manage data streams with full- and low-speed devices, connected below a USB 2.0 hub, utilizing the split transaction protocol. Refer to the USB 2.0 Specification for the complete definition of the split transaction protocol.
PAGE 669
Universal Serial Bus Interface 13.6.12.1.1 Asynchronous—Do-Start-Split Do-Start-Split is the state which software must initialize a full- or low-speed asynchronous queue head. This state is entered from the Do-Complete-Split state only after a complete-split transaction receives a valid response from the transaction translator that is not a Nyet handshake. For queue heads in this state, the host controller executes a start-split transaction to the transaction translator.
PAGE 670
Universal Serial Bus Interface If the PID Code indicates an IN, then any of following responses are expected: • DATA0/1. On reception of data, the host controller ensures the PID matches the expected data toggle and checks CRC. If the packet is good, the host controller advances the state of the transfer (for example, moves the data pointer by the number of bytes received, decrements the BytesToTransfer field by the number of bytes received, and toggles the dt bit).
PAGE 671
Universal Serial Bus Interface and queue head data structure. The S and Cn labels indicate microframes where software can schedule start-splits and complete splits (respectively). Periodic Schedule Micro-Frame 0 7 1 S 2 C0 3 C1 4 5 6 7 0 1 C2 Case 1: Normal Case S C0 C1 C0 C1 C2 C1 C2 Case 2a: End of Frame S Case 2b: End of Frame S C0 Case 2c: End of Frame HS/FS/LS Bus Micro-Frame 6 7 B-Frame N–1 0 1 2 3 4 5 6 7 0 B-Frame N B-Frame N+1 H-Frame N Figure 13-53.
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Universal Serial Bus Interface Linkage repeats every 8 for remainder of frame list • • • Level 8 Level 4 Level 2 87 Level 1 (Root) 86 Periodic Frame List 43 85 42 84 21 • • • 10 83 41 82 20 40 81 80 80b Figure 13-54. General Structure of EHCI Periodic Schedule Utilizing Interrupt Spreading The periodic frame list is effectively the leaf level a binary tree, which is always traversed leaf to root. Each level in the tree corresponds to a 2N poll rate.
PAGE 673
Universal Serial Bus Interface • Frame C-mask. This is a bit-field where system software sets one or more bits corresponding to the microframes (within an H-Frame) that the host controller should execute complete-split transactions. The interpretation of this field is always qualified by the value of the SplitXState bit in the Status field of the queue head.
PAGE 674
Universal Serial Bus Interface • IN or an OUT). Refer to the EHCI Specification for a complete list of additional conditions that must be met in general for the host controller to issue a bus transaction. Note that the host controller must not execute a Start-split transaction while executing in Recovery Path mode. Refer to the EHCI Specification for special handling when in Recovery Path mode. Stop traversing the recovery path when it encounters an FSTN that is a Restore indicator.
PAGE 675
Universal Serial Bus Interface Pointer. At the same time, it sets an internal flag indicating that it is now in Recovery Path mode (the recovery path is annotated in Figure 13-55 with a large dashed line). The host controller continues traversing data structures on the recovery path and executing only those bus transactions as noted above, on the recovery path until it reaches Restore FSTN (Restore-N). Restore-N.Back Path Link Pointer.
PAGE 676
Universal Serial Bus Interface 13.6.12.2.4 Tracking Split Transaction Progress for Interrupt Transfers To correctly maintain the data stream, the host controller must be able to detect and report errors where data is lost. For interrupt-IN transfers, data is lost when it makes it into the USB 2.0 hub, but the USB 2.0 host system is unable to get it from the USB 2.0 hub and into the system before it expires from the transaction translator pipeline.
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Universal Serial Bus Interface corresponds to the current microframe number. For example, if the current microframe is 0, then cMicroFrameBit will equal 0b0000_0001. The variable cMicroFrameBit is used to compare against the S-mask and C-mask fields to determine whether the queue head is marked for a start- or complete-split transaction for the current microframe. Figure 13-56 illustrates how a complete interrupt split transaction is managed. There are two phases to each split transaction.
PAGE 678
Universal Serial Bus Interface one of the following events occur: The transaction translator responds to a complete-split transaction with one of the following: • NAK. A NAK response is a propagation of the full- or low-speed endpoint's NAK response. • ACK. An ACK response is a propagation of the full- or low-speed endpoint's ACK response. Only occurs on an OUT endpoint. • DATA 0/1. Only occurs for INs. Indicates that this is the last of the data from the endpoint for this split transaction. • ERR.
PAGE 679
Universal Serial Bus Interface -----If to send a complete split in the previous microframe. So, if the 'previous bit' is set in C-mask, check C-prog-mask to make sure it happened. (previousBit bitAND QH.C-mask)then If not(previousBit bitAND QH.C-prog-mask) then rvalue = FALSE; End if End If -- If the C-prog-mask already has a one in this bit position, -- then an aliasing -- error has occurred.
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Universal Serial Bus Interface • • • • • • • See above description for testing for Last. The complete-split transaction received a NYET response from the transaction translator. Do not update any transfer state (except for C-prog-mask and FrameTag) and stay in this state. The host controller must not adjust Cerr on this response. Transaction Error (XactErr). Timeout, data CRC failure, etc. The Cerr field is decremented and the XactErr bit in the Status field is set.
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Universal Serial Bus Interface The queue is halted (an exit condition of the Execute Transaction state). The status field bits: Active bit is cleared and the Halted bit is set and the qTD is retired. Responses which are not enumerated in the list or which are received out of sequence are illegal and may result in undefined host controller behavior. The other possible combinations of tests A, B, C, and D may indicate that data or response was lost.
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Universal Serial Bus Interface • Rule 3: If transitioning from Do_Start Split to Do Complete Split and the current value of FRINDEX[2–0] is not 6, or currently in Do Complete Split and the current value of (FRINDEX[2–0]) is not 7, FrameTag is set to FRINDEX[7–3]. This accommodates all other cases in Figure 13-53. 13.6.12.2.9 Rebalancing the Periodic Schedule System software must occasionally adjust a periodic queue head's S-mask and C-mask fields during operation.
PAGE 683
Universal Serial Bus Interface a single isochronous scheduling model and adds the additional feature that all data received from the endpoint (per split transaction) must land into a contiguous buffer. 13.6.12.3.1 Split Transaction Scheduling Mechanisms for Isochronous Full-speed isochronous transactions are managed through a transaction translator's periodic pipeline.
PAGE 684
Universal Serial Bus Interface The B-Frame boundaries are marked with a large, bold, dashed line. The bottom of Figure 13-57 illustrates the relationship of an siTD to the H-Frame.
PAGE 685
Universal Serial Bus Interface • transaction spans more than one location in the periodic list.(for example, it takes two siTDs in adjacent periodic frame list locations to fully describe the scheduling for the split transaction). Although the scheduling of the split transaction may take two data structures, all of the complete-splits for each full-speed IN isochronous transaction must use only one data pointer. For this reason, siTDs contain a back pointer.
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Universal Serial Bus Interface usually also maps to one high-speed isochronous split transaction. The exception to this rule is the H-Frame boundary wrap cases mentioned above. The siTD data structure describes at most, one frame's worth of high-speed transactions and that description is strictly bounded within a frame boundary. Figure 13-58 illustrates some examples. On the top are examples of the full-speed transaction footprints for the boundary scheduling cases described above.
PAGE 687
Universal Serial Bus Interface • Software must ensure that for a single full-speed isochronous endpoint, there is never a start-split and complete-split in H-Frame, microframe 1. This is mandated as a rule so that case 2a and case 2b can be discriminated. According to the core USB specification, the long isochronous transaction illustrated in Case 2b, could be scheduled so that the start-split was in microframe 1 of H-Frame N and the last complete-split would need to occur in microframe 1 of H-Frame N+1.
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Universal Serial Bus Interface the complete-splits have not been executed in order. This can only occur due to system hold-offs where the host controller cannot get to the memory-based schedule. C-prog-mask is a simple bit-vector that the host controller sets a bit for each complete-split executed. The bit position is determined by the microframe (FRINDEX[2–0]) number in which the complete-split was executed. The host controller always checks C-prog-mask before executing a complete-split transaction.
PAGE 689
Universal Serial Bus Interface transaction state machine is used to manage the split-transaction protocol sequence. The host controller uses the fields defined in Section 13.6.12.3.2, “Tracking Split Transaction Progress for Isochronous Transfers,” plus the variable cMicroFrameBit defined in Section 13.6.12.2.5, “Split Transaction Execution State Machine for Interrupt,” to track the progress of an isochronous split transaction.
PAGE 690
Universal Serial Bus Interface The remainder of this section is specific to an isochronous OUT endpoint (that is, the I/O field indicates an OUT). When the host controller executes a start-split transaction for an isochronous OUT it includes a data payload in the start-split transaction. The memory buffer address for the data payload is constructed by concatenating siTD[Current Offset] with the page pointer indicated by the page select field (siTD[P]).
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Universal Serial Bus Interface • The siTD[TP] and siTD[T-count] fields are updated appropriately as defined in Table 13-70. These fields are then written back to the memory based siTD. The S-mask is fixed for the life of the current budget. As mentioned above, TP and T-count are set specifically in each siTD to reflect the data to be sent from this siTD.
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Universal Serial Bus Interface Algorithm Boolean CheckPreviousBit(siTD.C-prog-mask, siTD.C-mask, cMicroFrameBit) Begin Boolean rvalue = TRUE; previousBit = cMicroFrameBit rotate-right(1) -- Bit-wise anding previousBit with C-mask indicates whether there -- was an intent to send a complete split in the previous micro-- frame. So, if the 'previous bit' is set in C-mask, check -- C-prog-mask to make sure it happened. if previousBit bitAND siTD.C-mask then if not (previousBit bitAND siTD.
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Universal Serial Bus Interface • • • • • The complete-split transaction encounters a Timeout, CRC16 failure, etc. The siTD[Status] field XactErr field is set and the complete-split transaction must be retried immediately. The host controller must use an internal error counter to count the number of retries as a counter field is not provided in the siTD data structure. The host controller will not retry more than two times.
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Universal Serial Bus Interface 13.6.12.3.6 Complete-Split for Scheduling Boundary Cases 2a, 2b Boundary cases 2a and 2b (INs only) (see Figure 13-57) require that the host controller use the transaction state context of the previous siTD to finish the split transaction. Table 13-71 enumerates the transaction state fields. Table 13-71.
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Universal Serial Bus Interface is met the host controller immediately executes a start-split transaction and appropriately advances the transaction state of siTDX, then follows siTDX[Next Pointer] to the next schedule item. If the criterion is not met, the host controller simply follows siTDX[Next Pointer] to the next schedule item. Note that in the case of a 2b boundary case, the split-transaction of siTDX-1 will have its Active bit cleared when the host controller returns to the context of siTDX.
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Universal Serial Bus Interface The initial SplitXState of the first siTD is Do Start Split. The host controller will visit the first siTD eight times during frame X. The C-mask bits in microframes 0 and 1 are ignored because the state is Do Start Split. During microframe 4, the host controller determines that it can run a start-split (and does) and changes SplitXState to Do Complete Split. During microframes 6 and 7, the host controller executes complete-splits.
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Universal Serial Bus Interface 4. Set the Port Test Control field in the port under test PORTSC register to the value corresponding to the desired test mode. If the selected test is Test_Force_Enable, then USBCMD[RS] must then be transitioned back to one, in order to enable transmission of SOFs out of the port under test. 5. When the test is complete, system software must ensure the host controller is halted (HCH bit is a one) then it terminates and exits test mode by setting USBCMD[RST]. 13.6.
PAGE 698
Universal Serial Bus Interface NOTE The only method software should use for acknowledging an interrupt is by transitioning the appropriate status bits in the USBSTS register from a one to a zero. 13.6.14.1 Transfer/Transaction Based Interrupts These interrupt sources are associated with transfer and transaction progress. They are all dependent on the next interrupt threshold. 13.6.14.1.
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Universal Serial Bus Interface endpoint if it is using a queue head. Maximum length is defined as the minimum of total bytes to transfer and maximum packet size. The Cerr field is not decremented for a packet babble condition (only applies to queue heads). A babble condition also exists if IN transaction is in progress at High-speed EOF2 point. This is called a frame babble. A frame babble condition is recorded into the appropriate schedule data structure.
PAGE 700
Universal Serial Bus Interface 13.6.14.1.4 USB Interrupt (Interrupt on Completion (IOC)) Transfer Descriptors (iTDs, siTDs, and queue heads (qTDs)) contain a bit that can be set to cause an interrupt on their completion. The completion of the transfer associated with that schedule item causes USBSTS[UI] (USB interrupt) to be set. In addition, if a short packet is encountered on an IN transaction associated with a queue head, then this event also causes USBINT to be set.
PAGE 701
Universal Serial Bus Interface 13.6.14.2.4 Host System Error The host controller is a bus master and any interaction between the host controller and the system may experience errors. The type of host error may be catastrophic to the host controller making it impossible for the host controller to continue in a coherent fashion. Behavior for these types of errors is to halt the host controller. Host-based error must result in the following actions: • USBCMD[RS] is cleared.
PAGE 702
Universal Serial Bus Interface The USB DR module includes DCD software called the USB 2.0 Device API. The device API provides an easy to use Application Program Interface for developing device (peripheral) applications. The device API incorporates and abstracts for the application developer all of the elements of the program interface.
PAGE 703
Universal Serial Bus Interface Figure 13-61 shows the Endpoint Queue Head structure.
PAGE 704
Universal Serial Bus Interface Table 13-75. Endpoint Capabilities/Characteristics (continued) Bits Name 28–27 — 26–16 Description Reserved, should be cleared. These bit reserved for future use and should be cleared. Maximum Maximum packet length. This directly corresponds to the maximum packet size of the associated endpoint Packet (wMaxPacketSize). The maximum value this field may contain is 0x400 (1024). Length 15 ios 14–0 Interrupt on setup (IOS).
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Universal Serial Bus Interface Table 13-77 describes the multiple mode control fields. Table 13-77. Multiple Mode Control DWord Bits Description 1 31–0 Setup Buffer 0. This buffer contains bytes 3 to 0 of an incoming setup buffer packet and is written by the device controller to be read by software. 2 31–0 Setup Buffer 1. This buffer contains bytes 7 to 4 of an incoming setup buffer packet and is written by the device controller to be read by software. 13.7.
PAGE 706
Universal Serial Bus Interface Table 13-79 describes the next dTD token fields. Table 13-79. dTD Token Bits 31 Description Reserved, should be cleared. Bit reserved for future use and should be cleared. 30–16 Total Bytes. This field specifies the total number of bytes to be moved with this transfer descriptor. This field is decremented by the number of bytes actually moved during the transaction and only on the successful completion of the transaction.
PAGE 707
Universal Serial Bus Interface Table 13-81. Buffer Pointer Page 1 Bits Description 31–12 Buffer Pointer. Selects the page offset in memory for the packet buffer. Non virtual memory systems will typically set the buffer pointers to a series of incrementing integers. 11 10–0 Reserved Frame Number. Written by the device controller to indicate the frame number in which a packet finishes. This is typically be used to correlate relative completion times of packets on an ISO endpoint. Table 13-82.
PAGE 708
Universal Serial Bus Interface NOTE Transitioning from host mode to device mode requires a device controller reset before modifying USBMODE. 2. 3. 4. 5. Optionally modify the BURSTSIZE register. Program PORTSC[PTS] if using a non-ULPI PHY. Set CONTROL[USB_EN] Allocate and initialize device queue heads in system memory Minimum: Initialize device queue heads 0 Tx and 0 Rx. NOTE All device queue heads must be initialized for control endpoints before the endpoint is enabled.
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Universal Serial Bus Interface Inactive State Active State Powered Set Run/Stop Bit to Run Mode Power Interruption Attach Reset Bus Inactive When the Host Resets the Device Returns to the Default State Default FS/HS Suspend FS/HS Bus Activity Address Assigned Bus Inactive Suspend FS/HS Address FS/HS Device Deconfigured Device Configured Bus Activity Bus Inactive Suspend FS/HS Configured FS/HS Bus Activity Software Only State Figure 13-63. USB 2.
PAGE 710
Universal Serial Bus Interface As a result of entering the address state, the device address register (DEVICEADDR) must be programmed by the DCD. Entry into the configured indicates that all endpoints to be used in the operation of the device have been properly initialized by programming the ENDPTCTRLn registers and initializing the associated queue heads. 13.8.2.1 Bus Reset A bus reset is used by the host to initialize downstream devices.
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Universal Serial Bus Interface 13.8.2.2 Suspend/Resume This section discusses the suspend and resume functions. 13.8.2.2.1 Suspend Description In order to conserve power, USB_DR automatically enters the suspended state when no bus traffic has been observed for a specified period. When suspended, the USB_DR maintains any internal status, including its address and configuration.
PAGE 712
Universal Serial Bus Interface between the host and the device. The endpoint address is specified by the combination of the endpoint number and the endpoint direction. The channel between the host and an endpoint at a specific device represents a data pipe. Endpoint 0 for a device is always a control type data channel used for device discovery and enumeration. Other types of endpoints support by USB include bulk, interrupt, and isochronous.
PAGE 713
Universal Serial Bus Interface The first occasion is the functional stall, which is a condition set by the DCD as described in the USB 2.0 device framework (Chapter 9). A functional stall is only used on non-control endpoints and can be enabled in the device controller by setting the endpoint stall bit in the ENDPTCTRLn register associated with the given endpoint and the given direction.
PAGE 714
Universal Serial Bus Interface In normal operation, the USB_DR checks the DATA0/DATA1 bit against the data toggle to determine if the packet is valid. If Data PID does not match the data toggle state bit maintained by the device controller for that endpoint, the Data toggle is considered not valid. If the data toggle is not valid, the device controller assumes the packet was already received and discards the packet (not reporting it to the DCD).
PAGE 715
Universal Serial Bus Interface Note as part of the architecture, the FIFO for the receive endpoints is not partitioned into multiple channels like the transmit FIFO. Thus, the size of the RX FIFO does not scale with the number of endpoints. 13.8.3.4 Interrupt/Bulk Endpoint Operational Model The behaviors of the device controller for interrupt and bulk endpoints are identical. All valid IN and OUT transactions to bulk pipes will handshake with a NAK unless the endpoint had been primed.
PAGE 716
Universal Serial Bus Interface RX-dTD is complete when: • All packets described in dTD were successfully received. *** Total bytes in dTD will equal zero when this occurs. • A short packet (number of bytes < maximum packet length) was received. *** This is a successful transfer completion; DCD must check Total Bytes in dTD to determine the number of bytes that are remaining. From the total bytes remaining in the dTD, the DCD can compute the actual bytes received.
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Universal Serial Bus Interface 13.8.3.5 Control Endpoint Operation Model This section discusses the control endpoint operation model. 13.8.3.5.1 Setup Phase All requests to a control endpoint begin with a setup phase followed by an optional data phase and a required status phase. The USB_DR will always accept the setup phase unless the setup lockout is engaged. The setup lockout will engage so that future setup packets are ignored.
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Universal Serial Bus Interface After priming the packet, the DCD must verify a new setup packet has not been received by reading the ENDPTSETUPSTAT register immediately verifying that the prime had completed. A prime will complete when the associated bit in the ENDPTPRIME register is zero and the associated bit in the ENDPTSTATUS register is a one. If a prime fails, that is, The ENDPTPRIME bit goes to zero and the ENDPTSTATUS bit is not set, then the prime has failed.
PAGE 719
Universal Serial Bus Interface Table 13-89. Control Endpoint Bus Response Matrix (continued) Endpoint State Token Type Setup Lockout Stall Not Primed Primed Underflow Overflow Ping STALL NAK ACK N/A N/A N/A Invalid Ignore Ignore Ignore Ignore Ignore Ignore 1 SYSERR—System error should never occur when the latency FIFOs are correctly sized and the DCD is responsive. 2 Force Bit Stuff Error.
PAGE 720
Universal Serial Bus Interface The transaction error bit set in the status field indicates a fulfillment error condition. When a fulfillment error occurs, the frame after the transfer failed to complete wholly, the device controller will force retire the ISO-dTD and move to the next ISO-dTD. It is important to note that fulfillment errors are only caused due to partially completed packets. If no activity occurs to a primed ISO-dTD, the transaction will stay primed indefinitely.
PAGE 721
Universal Serial Bus Interface must write the prime bit. The USB_DR will prime the isochronous endpoint in (micro)frame N – 1 so that the device controller will execute delivery during (micro)frame N. CAUTION Priming an endpoint towards the end of (micro)frame N – 1 will not guarantee delivery in (micro)frame N. The delivery may actually occur in (micro)frame N + 1 if device controller does not have enough time to complete the prime before the SOF for packet N is received. 13.8.3.6.
PAGE 722
Universal Serial Bus Interface The device queue head (dQH) points to the linked list of transfer tasks, each depicted by the device Transfer Descriptor (dTD). An area of memory pointed to by ENDPOINTLISTADDR contains a group of all dQHs in a sequential list as shown in Figure 13-64. The even elements in the list of dQH’s are used for receive endpoints (OUT/SETUP) and the odd elements are used for transmit endpoints (IN/INTERRUPT).
PAGE 723
Universal Serial Bus Interface NOTE After the acknowledge has occurred, the DCD must not attempt to access the setup buffer in the dQH - RX. Only the local software copy should be examined. 3. Check for pending data or status dTD’s from previous control transfers and flush if any exist as discussed in Section 13.8.5.5, “Flushing/De-Priming an Endpoint.” NOTE It is possible for the device controller to receive setup packets before previous control transfers complete.
PAGE 724
Universal Serial Bus Interface Allocate 8-DWord dTD block of memory aligned to 8-DWord boundaries. Example: bit address 4–0 would be equal to ‘00000’. Write the following fields: 1. Initialize first seven DWords to ‘0’. 2. Set the terminate bit to ‘1’. 3. Fill in total bytes with transfer size. 4. Set the interrupt on complete if desired. 5. Initialize the status field with the active bit set to ‘1’ and all remaining status bits set to ‘0’. 6.
PAGE 725
Universal Serial Bus Interface Complete bit was set or alternately, the DCD can poll the endpoint complete register to find when the dTD had been executed. After a dTD has been executed, DCD can check the status bits to determine success or failure. CAUTION Multiple dTD can be completed in a single endpoint complete notification. After clearing the notification, DCD must search the dTD linked list and retire all dTDs that have finished (Active bit cleared).
PAGE 726
Universal Serial Bus Interface 13.8.5.6 Device Error Matrix Table 13-91 summarizes packet errors that are not automatically handled by the USB controller. Table 13-91. Device Error Matrix Direction Packet Type Data Buffer Error Bit Transaction Error Bit Overflow ** RX Any 1 0 ISO Packet Error RX ISO 0 1 Both ISO 0 1 Error ISO Fulfillment Error Notice that the device controller handles all errors on Bulk/Control/Interrupt Endpoints except for a data buffer overflow.
PAGE 727
Universal Serial Bus Interface Table 13-93. Interrupt Handling Order (continued) Execution Order 1 Interrupt Action 1b USB Interrupt ENDPTCOMPLETE Handle completion of dTD as indicated in Section 13.8.4, “Managing Queue Heads”. 2 SOF Interrupt Action as deemed necessary by application. This interrupt may not have a use in all applications. It is likely that multiple interrupts to stack up on any call to the Interrupt Service Routine AND during the Interrupt Service Routine. 13.8.6.
PAGE 728
Universal Serial Bus Interface • • • Device operation—In host mode, the device operational registers are generally disabled and thus device mode is mostly transparent when in host mode. However, there are a couple exceptions documented in the following sections. Embedded design interface—The module does not have a PCI interface and therefore the PCI configuration registers described in the EHCI specification are not applicable.
PAGE 729
Universal Serial Bus Interface low-speed devices or hubs. Table 13-96 summarizes the functional differences between EHCI and EHCI with embedded TT. Table 13-96. Functional Differences Between EHCI and EHCI with Embedded TT Standard EHCI EHCI with Embedded Transaction Translator After port enable bit is set following a connection and After port enable bit is set following a connection and reset sequence, reset sequence, the device/hub is assumed to be HS. the device/hub speed is noted from PORTSC.
PAGE 730
Universal Serial Bus Interface bus between EHCI host controller driver and the USB FS/LS bus. These sections will briefly discuss the operational model for how the EHCI and transaction translator operational models are combined without the physical bus between. The following sections assume the reader is familiar with both the EHCI and USB 2.0 transaction translator operational models. 13.9.1.5.
PAGE 731
Universal Serial Bus Interface 13.9.1.5.3 Asynchronous Transaction Scheduling and Buffer Management The following Universal Serial Bus Revision 2.0 Specification items are implemented in the embedded transaction translator: • USB 2.0–11.17.3 — Sequencing is provided and a packet length estimator ensures no full-speed/low-speed packet babbles into SOF time. • USB 2.0–11.17.4 — Transaction tracking for 2 data pipes. • USB 2.0–11.17.5 — Clear_TT_Buffer capability provided 13.9.1.5.
PAGE 732
Universal Serial Bus Interface 13.9.3 Non-Zero Fields the Register File Some of the reserved fields and reserved addresses in the capability registers and operational registers have use in device mode, the following must be adhered to: • Write operations to all EHCI reserved fields (some of which are device fields in the DR module) in the operation registers should always be written to zero. This is an EHCI requirement of the device controller driver that must be adhered to.
PAGE 733
Universal Serial Bus Interface there are counter already present in the design that can count the 10 msec reset pulse to alleviate the requirement of the software to measure this duration. Therefore, the basic connection is then summarized as the following: • [Port Change Interrupt] Port connect change occurs to notify the host controller driver that a device has attached. • Software shall write a ‘1’ to the reset the device. • Software shall write a ‘0’ to the reset the device after 10 msec.
PAGE 734
Universal Serial Bus Interface 13.10 Timing Diagrams This section contains diagrams showing the basic operation of the ULPI interface. For a more detailed description refer to the ULPI Specifications. Figure 13-66 shows ULPI timing. PHY_CLK TSC THC DIR/NXT TSD THD DATA (from PHY) TDC TDC STP TDD DATA (to PHY) Figure 13-66. ULPI Timing Table 13-98 summarizes the ULPI timing parameters. Table 13-98.
PAGE 735
Universal Serial Bus Interface Figure 13-67 shows the diagram for the sending of RX CMD. PHY_CLK turn around DATA turn around turn around turn around RX CMD RX CMD RX CMD DIR STP NXT Figure 13-67. Sending of RX CMD Figure 13-68 shows ULPI data transmit—NOPID. PHY_CLK DATA TX CMD(NOPID) D0 D1 D2 DIR STP NXT Figure 13-68. ULPI Data Transmit (NOPID) MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev.
PAGE 736
Universal Serial Bus Interface Figure 13-69 shows ULPI data transmit—PID. PHY_CLK DATA TX CMD(PID) D1 D2 D3 DIR STP NXT Figure 13-69. ULPI Data Transmit (PID) Figure 13-70 shows ULPI data receive. PHY_CLK DATA RX CMD PID D1 RX CMD D2 D3 DIR STP NXT Figure 13-70. ULPI Data Receive MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev.
PAGE 737
Universal Serial Bus Interface Figure 13-71 shows ULPI register write. PHY_CLK DATA TX CMD(RegWr) DATA DIR STP NXT Figure 13-71. ULPI Register Write Figure 13-72 shows ULPI register read. PHY_CLK DATA TX CMD(RegWr) DATA DIR STP NXT Figure 13-72. ULPI Register Read MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev.
PAGE 738
Universal Serial Bus Interface MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev.
PAGE 739
Chapter 14 PCI Express Interface Controller The MPC8308 PCI Express interface is compatible with the PCI Express™ Base Specification, Revision 1.0a (available from http://www.pcisig.org). It is beyond the scope of this manual to document the intricacies of the PCI Express protocol. This chapter describes the PCI Express controller of this device and provides a basic description of the PCI Express protocol. The specific emphasis is directed at how the device implements the PCI Express specification.
PAGE 740
PCI Express Interface Controller Figure 14-1 is a high-level block diagram of the PCI Express controller. CSB Bridge WDMA CSB Interface RDMA PCI Express Core Interface Configuration Registers Message Manager RX TX Transaction Layer RX TX Data Link Layer PCI Express Core Configuration Registers RX TX SerDes Interface MAC Layer SerDes Configuration Registers PCI Express Link Figure 14-1.
PAGE 741
PCI Express Interface Controller As an initiator, the device supports memory read and write operations with a maximum payload of 128 bytes and I/O transactions. In addition, outbound configurations are supported if the device is in RC mode. As a target interface, the device accepts read and write operations to local memory space. Furthermore, as an EP device, the device accepts configuration transactions to the internal PCI Express configuration registers. Inbound I/O transactions are not supported. 14.1.
PAGE 742
PCI Express Interface Controller 14.1.3 Features The following is a list of PCI Express controller features: • Designed to be compatible with the PCI Express Base Specification, Version 1.
PAGE 743
PCI Express Interface Controller 14.1.4.3 Reference Clock The reference clock for the PCI Express PHY is set to 100 MHz upon POR. To change the reference clock frequency after POR, program the SRDSCR4 (see Section 15.3.5, “SerDes Control Register 4 (SRDSCR4)”) and initiate a SerDes PHY reset sequence. By default, PCI Express controller clock is the same as CSB clock. 14.
PAGE 744
PCI Express Interface Controller • • Mixed indicates a combination of access types. Special is used when no other category applies. In this case, the register figure and field description table should be read carefully. Memory-mapped registers for PCI Express controller begin at block base address 0x0_9000. Table 14-2 below lists the address ranges for each type of register. Undefined address spaces are reserved. Table 14-2.
PAGE 745
PCI Express Interface Controller Table 14-3. PCI Express Memory Map (continued) Offset Register Access Reset Section/Page R/W 0x00 14.4.1.7/14-19 PCI Express—Block Base Address 0x0_9000 0x00C PCI Express Cache Line Size Register 0x00D PCI Express Latency Timer Register R 0x00 14.4.1.8/14-19 0x00E PCI Express Header Type Register R 0x00 (EP mode) 0x01 (RC mode) 14.4.1.9/14-20 0x00F PCI Express BIST Register R 0x00 14.4.1.
PAGE 746
PCI Express Interface Controller Table 14-3. PCI Express Memory Map (continued) Offset Register Access Reset Section/Page R 0x044 14.4.3.16/14-34 R/W 0x0000 14.4.3.17/14-35 — — — R/W 0x0000 14.4.3.18/14-35 PCI Express—Block Base Address 0x0_9000 0x034 PCI Express Capabilities Pointer Register 0x03C PCI Express Interrupt Line Register 0x03D Reserved 0x03E PCI Express Bridge Control Register (RC mode only) 0x044 PCI Express Power Management Capability ID Register R 0x01 14.4.4.
PAGE 747
PCI Express Interface Controller Table 14-3. PCI Express Memory Map (continued) Offset Register Access Reset Section/Page PCI Express—Block Base Address 0x0_9000 0x110 PCI Express Correctable Error Status Register w1c 0x0000_0000 14.4.5.5/14-56 0x114 PCI Express Correctable Error Mask Register R/W 0x0000_0000 14.4.5.6/14-57 0x118 PCI Express Advanced Error Capabilities and Control Register R/W 0x0000_00A0 14.4.5.7/14-58 0x11C PCI Express Header Log Register R 0x0000_0000 14.4.5.
PAGE 748
PCI Express Interface Controller Table 14-3. PCI Express Memory Map (continued) Offset Register Access Reset Section/Page 0x0000_0400 14.4.7.
PAGE 749
PCI Express Interface Controller Table 14-3. PCI Express Memory Map (continued) Offset Register Access Reset Section/Page — — — PCI Express—Block Base Address 0x0_9000 0x9AC Reserved 0xA40 PCI Express Read DMA Control Register (PEX_RDMA_CTRL) R/W 0x0000_0000 14.5.5.4/14-86 0xA44 PCI Express Read DMA first Address Register (PEX_RDMA_ADDR) R/W 0x0000_0000 14.5.5.5/14-86 0xA48 PCI Express Read DMA Status Register (PEX_RDMA_STAT) w1c 0x0000_0000 14.5.5.
PAGE 750
PCI Express Interface Controller Table 14-3. PCI Express Memory Map (continued) Offset Register Access Reset Section/Page w1c 0x0000_0000 14.5.8.8/14-101 R/W 0x0000_0000 14.5.9.
PAGE 751
PCI Express Interface Controller Table 14-3. PCI Express Memory Map (continued) Offset Register Access Reset Section/Page PCI Express—Block Base Address 0x0_9000 0xDE4 PCI Express EP Inbound Window Translation Address Register 1 (PEX_EPIWTAR1) R/W 0x0000_0000 14.5.11.1/14-108 0xDE8 PCI Express EP Inbound Window Translation Address Register 2 (PEX_EPIWTAR2) R/W 0x0000_0000 14.5.11.
PAGE 752
PCI Express Interface Controller 1 MPC8308 does not support these registers in accordance with the PCIe specification. For more information, see PCI Express Base Specification, March 28, 2005 (Page 357-358). These registers are mentioned here only for completeness. It is recommended not to change the reset values of these registers. 14.
PAGE 753
PCI Express Interface Controller NOTE The registers described in this section use little-endian byte ordering. Software running on the local processor in big-endian mode must byte-swap the data. No byte swapping occurs when the registers are accessed from the PCI Express bus. 14.4.1.1 PCI Express Vendor ID Register The vendor ID register, shown in Figure 14-3, identifies the manufacturer of the device.
PAGE 754
PCI Express Interface Controller the PCI Express device control register described in Section 14.4.4.10, “PCI Express Device Control Register,” and the advance error reporting capability structure described in Section 14.4.5.1, “PCI Express Advanced Error Reporting Capability ID Register,” through Section 14.4.5.11, “PCI Express Error Source Identification Register.
PAGE 755
PCI Express Interface Controller 14.4.1.4 PCI Express Status Register The status register, shown in Figure 14-6, records status information for PCI Express events.
PAGE 756
PCI Express Interface Controller 14.4.1.5 PCI Express Revision ID Register The revision ID register, shown in Figure 14-7, identifies the revision of the device. Offset 0x008 Access: Read-only 7 0 R Revision ID W Reset Revision specific Figure 14-7. PCI Express Revision ID Register . Table 14-8 describes the revision ID register fields. Table 14-8. PCI Express Revision ID Register Fields Description Bits Name 7–0 Revision ID 14.4.1.6 Description Revision specific. The value is 0x10.
PAGE 757
PCI Express Interface Controller . Table 14-9 describes the class code register fields. Table 14-9. PCI Express Class Code Register Fields Description Bits Name 23–16 Base Class 0x0B—Processor 15–8 Subclass 0x20—PowerPC 7–0 Description Programming 0x00—RC mode Interface 0x00—EP mode 14.4.1.7 PCI Express Cache Line Size Register The cache line size register, shown in Figure 14-9, is provided for legacy compatibility (PCI 2.3); it is not used for PCI Express device functionality.
PAGE 758
PCI Express Interface Controller Table 14-11 describes the PCI Express latency timer register (PLTR). Table 14-11. PCI Express Latency Timer Register Fields Description Bits 7–0 Name Description Latency Timer Note that for PCI Express operation this register is ignored. 14.4.1.9 PCI Express Header Type Register The PCI Express header type register, shown in Figure 14-11, identifies the layout of the PCI Express-compatible header.
PAGE 759
PCI Express Interface Controller 14.4.1.10 PCI Express BIST Register The BIST register is optional and reserved on the PCI Express controller. 14.4.2 Type 0 PCI Express-Compatible Configuration Header Registers The type 0 header is shown in Figure 14-12.
PAGE 760
PCI Express Interface Controller attributes are programmed by an indirect registers access, using the PCI Express BAR Configuration Registers. For further details see Section 14.4.7, “PCI Express BAR Configuration Registers (EP Mode).
PAGE 761
PCI Express Interface Controller 14.4.2.1.2 Base Address Registers 2 and 4 (BAR2/BAR4) BAR2 and BAR4, shown in Figure 14-14, define the lower portion of the 64-bit inbound memory windows. Offset 0x018 (EP mode only) 0x020 (EP mode only) Access: Mixed 31 12 11 R ADDRESS W 4 — 3 PREF Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 TYPE 1 0 0 MemSp 0 Figure 14-14.
PAGE 762
PCI Express Interface Controller 14.4.2.2 PCI Express Subsystem Vendor ID Register (EP Mode Only) The PCI Express subsystem vendor ID register, shown in Figure 14-16, identifies the subsystem. Offset 0x02C (EP mode only) Access: Read-only 15 0 R Subsystem Vendor ID W Reset All zeros Figure 14-16. PCI Express Subsystem Vendor ID Register Table 14-16 describes the PCI Express subsystem vendor ID register. Table 14-16.
PAGE 763
PCI Express Interface Controller 14.4.2.4 PCI Express Capabilities Pointer Register The PCI Express capabilities pointer register, shown in Figure 14-18, identifies additional functionality supported by the device. Offset 0x034 Access: Read-only 7 0 R Capabilities Pointer W Reset 0 1 0 0 0 1 0 0 Figure 14-18. PCI Express Capabilities Pointer Register Table 14-18 describes the PCI Express capabilities pointer. Table 14-18.
PAGE 764
PCI Express Interface Controller 14.4.2.6 PCI Express Minimum Grant Register (EP Mode Only) This register does not apply to PCI Express. It is present for legacy purposes. Offset 0x03E (EP mode only) Access: Read-only 7 0 R MIN_GNT W Reset All zeros Figure 14-20. PCI Express Minimum Grant Register (MAX_GNT) Table 14-20. PCI Express MInimum Grant Register Fields Description Bits 7–0 Name Description MIN_GNT Does not apply for PCI Express. 14.4.2.
PAGE 765
PCI Express Interface Controller 14.4.3 Type 1 PCI-Compatible Configuration Header Registers The type 1 header is shown in Figure 14-22.
PAGE 766
PCI Express Interface Controller 14.4.3.2 PCI Express Secondary Bus Number Register (RC Mode Only) The secondary bus number register is shown in Figure 14-24. Offset 0x019 Access: Read/Write 7 0 R Secondary Bus Number W Reset All zeros Figure 14-24. PCI Express Secondary Bus Number Register Table 14-23 describes the secondary bus number register fields. Table 14-23. PCI Express Secondary Bus Number Register Fields Description Bits Name 7–0 Secondary Bus Number 14.4.3.
PAGE 767
PCI Express Interface Controller 14.4.3.5 PCI Express I/O Base Register (RC Mode Only) Note that this device does not support inbound I/O transactions. The I/O base register is shown in Figure 14-26. Offset 0x01C Access: Read-only 7 R 4 3 I/O Start Address 0 Address Decode Type W Reset All zeros Figure 14-26. PCI Express I/O Base Register Table 14-25 describes the I/O base register fields. Table 14-25.
PAGE 768
PCI Express Interface Controller 14.4.3.7 PCI Express Secondary Status Register (RC Mode Only) The PCI Express secondary status register is shown in Figure 14-28. Note that the errors in this register can be masked by corresponding bits in the secondary status interrupt mask register (PEX_SS_INTR_MASK) and that by default all the errors are masked. See Section 14.4.8.3, “Secondary Status Interrupt Mask Register (PEX_SS_INTR_MASK) (RC Mode Only),” for more information.
PAGE 769
PCI Express Interface Controller Table 14-28 describes the memory base register fields. Table 14-28. PCI Express Memory Base Register Fields Description Bits 15–4 Name Description Memory Specifies bits 31–20 of the non-prefetchable memory space start address. Typically used for specifying Base memory-mapped I/O space.
PAGE 770
PCI Express Interface Controller Table 14-30 describes the prefetchable memory base register fields. Table 14-30. PCI Express Prefetchable Memory Base Register Fields Description Bits 15–4 Name Description PF Memory Base Specifies bits 31–20 of the prefetchable memory space start address. 3–0 Address Decode Type Number of prefetchable memory address bits. 0x00 32-bit memory address decode 0x01 64-bit memory address decode All other settings reserved. 14.4.3.
PAGE 771
PCI Express Interface Controller Table 14-32 describes the PCI Express prefetchable memory base upper 32-bit register fields. Table 14-32. PCI Express Prefetchable Base Upper 32-Bit Register Fields Description Bits 31–0 Name Description PF Base Upper Specifies bits 64–32 of the prefetchable memory space start address when the address decode type 32 Bits field in the prefetchable memory base register is 0x01. 14.4.3.
PAGE 772
PCI Express Interface Controller 14.4.3.15 PCI Express I/O Limit Upper 16-Bit Register (RC Mode Only) Note that this device does not support inbound I/O transactions. The I/O limit upper 16-bit register is shown in Figure 14-36. Offset 0x032 Access: Read-only 15 0 R I/O Limit Upper 16 Bits W Reset All zeros Figure 14-36. PCI Express I/O Limit Upper 16-Bit Register Table 14-35 describes the I/O limit upper 16-bit register fields. Table 14-35.
PAGE 773
PCI Express Interface Controller 14.4.3.17 PCI Express Interrupt Line Register The PCI Express interrupt line register, shown in Figure 14-38, is used by device drivers and OS software to communicate interrupt line routing information. Values in this register are programmed by system software and are system-specific. Offset 0x03C Access: Read/Write 7 0 R Interrupt Line W Reset All zeros Figure 14-38.
PAGE 774
PCI Express Interface Controller 14.4.4 PCI Express-Compatible Device-Specific Configuration Space Registers The PCI Express-compatible device-specific configuration space is a PCI Express-compatible configuration space from 0x040 to 0x0FF (just above the 64-byte PCI Express-compatible configuration header). Address Offset (Hex) Reserved 000 PCI-Compatible Configuration Header (See Section 14.4.1, “Common PCI Express-Compatible Configuration Header Registers,” for more information.
PAGE 775
PCI Express Interface Controller 14.4.4.1 PCI Express Power Management Capability ID Register The PCI Express power management capability ID register is shown in Figure 14-41. Offset 0x044 Access: Read-only 7 0 R Power Mgmt Capability ID W Reset 0 0 0 0 0 0 0 1 Figure 14-41. PCI Express Power Management Capability ID Register Table 14-39 describes the PCI Express power management capability ID fields. Table 14-39.
PAGE 776
PCI Express Interface Controller 14.4.4.3 PCI Express Power Management Capabilities Register The PCI Express power management capabilities register is shown in Figure 14-43. Offset 0x046 Access: Read-only 15 11 R PME Support 10 9 D2 D1 1 1 8 6 5 AUX Curr DSI 4 3 2 — PME CLK 0 Version W Reset 0 1 1 1 1 0 0 0 0 0 0 0 1 0 Figure 14-43. PCI Express Power Management Capabilities Register Table 14-41 describes the PCI Express power management capabilities register fields.
PAGE 777
PCI Express Interface Controller Table 14-42. PCI Express Power Management Status and Control Register Fields Description (continued) Bits Name 8 PME_EN 7–2 — 1–0 Power State 14.4.4.5 Description PME Enable Reserved Power state. Indicates the current power state of the function. 00 D0 01 D1 02 D2 03 D3 PCI Express Power Management Data Register The PCI Express power management data register is shown in Figure 14-45. Offset 0x04B Access: Read-only 7 0 R Data W Reset All zeros Figure 14-45.
PAGE 778
PCI Express Interface Controller Table 14-44 describes the PCI Express capability ID register fields. Table 14-44. PCI Express Capability ID Register Fields Description Bits 7–0 Name Description PCI Express Capability ID PCI Express = 0x10 14.4.4.7 PCI Express Next Capabilities Pointer Register The PCI Express next capabilities pointer register is shown in Figure 14-47.
PAGE 779
PCI Express Interface Controller Table 14-46. PCI Express Capabilities Register Fields Description (continued) Bits Name 7–4 Device/Port Type 3–0 Version 14.4.4.9 Description 0100 (RC mode) 0000 (EP mode) Indicates PCI-SIG defined PCI Express capability structure version number. 0x1identifies version 1.0a. PCI Express Device Capabilities Register The PCI Express device capabilities register is shown in Figure 14-49.
PAGE 780
PCI Express Interface Controller Table 14-47. PCI Express Device Capabilities Register Fields Description (continued) Bits Name 4–3 PHAN_FCT 2–0 Description Phantom functions supported MAX_PL_SIZE_SUP Maximum payload size supported. 000 = 128 bytes 14.4.4.10 PCI Express Device Control Register The PCI Express device control register is shown in Figure 14-50.
PAGE 781
PCI Express Interface Controller 14.4.4.11 PCI Express Device Status Register The PCI Express device status register is shown in Figure 14-51. Offset 0x056 Access: Mixed 15 6 R — W Reset 5 4 3 TP APD URD FED NFED CED 2 1 w1c w1c w1c 0 w1c All zeros Figure 14-51. PCI Express Device Status Register Table 14-49 describes the PCI Express device status register fields. Table 14-49.
PAGE 782
PCI Express Interface Controller Table 14-50 describes the PCI Express link capabilities register fields. Table 14-50. PCI Express Link Capabilities Register Fields Description Bits Name Description 31–24 Port Number 23–18 — 17–15 L1_EX_LAT L1 exit latency. 0b111 indicates more than 64 microseconds 14–12 L0s_EX_LAT L0s exit latency. 0b101 indicates 1024 ns to less than 2048 ns 11–10 ASPM 9–4 MAX_LINK_W 3–0 MAX_LINK_SP Maximum link speed, 0b0001 indicates 2.
PAGE 783
PCI Express Interface Controller 14.4.4.14 PCI Express Link Status Register The PCI Express link status register is shown in Figure 14-54. Offset 0x05E Access: Read-only 15 13 R — 12 11 10 SCC LT — 0 0 0 9 4 3 NEG_LINK_W 0 LINK_SP W Reset 0 0 0 0 0 0 0 0 1 0 0 0 1 Figure 14-54. PCI Express Link Status Register Table 14-52 describes the PCI Express link status register fields. Table 14-52.
PAGE 784
PCI Express Interface Controller Table 14-53 describes the PCI Express link status register fields. Table 14-53. PCI Express Slot Capabilities Register Fields Description Bits Name Description 31–19 Physical Slot Number 18–17 — 16–15 SPLS Slot power limit scale.
PAGE 785
PCI Express Interface Controller Table 14-54. PCI Express Slot Control Register Fields Description (continued) Bits Name Description 2 MRLSCE MRL sensor changed enable 1 PFDE Power fault detected enable 0 ABPE Attention button pressed enable 14.4.4.17 PCI Express Slot Status Register The PCI Express slot status register is shown in Figure 14-57.
PAGE 786
PCI Express Interface Controller 14.4.4.18 PCI Express Root Control Register (RC Mode Only) The PCI Express root control register is shown in Figure 14-58. Offset 0x068 Access: Read/Write 15 4 R — W 3 2 1 0 PMEIE SEFEE SENFEE SECEE Reset All zeros Figure 14-58. PCI Express Root Control Register Table 14-56 describes the PCI Express root control register fields. Table 14-56. PCI Express Root Control Register Fields Description Bits Name 15–4 — 3 PMEIE PME interrupt enable.
PAGE 787
PCI Express Interface Controller Table 14-57. PCI Express Root Status Register Fields Description (continued) Bits Name 16 PMES 15–0 Description PME status. PME Requestor ID PME requestor ID. 14.4.4.20 PCI Express MSI Message Capability ID Register (EP Mode Only) The PCI Express MSI message capability ID register is shown in Figure 14-60. Offset 0x070 Access: Read-only 7 0 R MSI Message Capability ID W Reset 0 0 0 0 0 1 0 1 Figure 14-60.
PAGE 788
PCI Express Interface Controller Table 14-59 describes the PCI Express MSI message control register fields. Table 14-59. PCI Express MSI Message Control Register Fields Description Bits Name 15–8 — 7 Description Reserved 64AC 64-bit address capable 6–4 MME Multiple message enable 3–1 MMC Multiple message capable 0 MSIE MSI enable 14.4.4.22 PCI Express MSI Message Address Register (EP Mode Only) The PCI Express MSI message address register is shown in Figure 14-62.
PAGE 789
PCI Express Interface Controller 14.4.4.24 PCI Express MSI Message Data Register (EP Mode Only) The PCI Express MSI message data register is shown in Figure 14-64. Offset 0x07C Access: Read/Write 15 0 R Message Data W Reset All zeros Figure 14-64. PCI Express MSI Message Data Register Table 14-62 describes the PCI Express MSI message data register fields. Table 14-62.
PAGE 790
PCI Express Interface Controller 14.4.5 PCI Express Extended Configuration Space Figure 14-65 shows the PCI Express extended configuration space. Address Offset (Hex) Reserved 000 PCI Express-Compatible Configuration Header (See Section 14.4.1, “Common PCI Express-Compatible Configuration Header Registers,” for more information.) 03F 040 PCI Express-Compatible Device-Specific Configuration Space (See Section 14.4.
PAGE 791
PCI Express Interface Controller 14.4.5.1 PCI Express Advanced Error Reporting Capability ID Register The PCI Express advanced error reporting capability ID register is shown in Figure 14-66. Offset 0x100 Access: Read-only 31 20 R 19 Next Capability Pointer 16 Capability Version W Reset 0 0 0 1 0 0 1 1 1 0 0 0 0 0 0 15 1 0 R Capability ID W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Figure 14-66.
PAGE 792
PCI Express Interface Controller Table 14-64 describes the PCI Express uncorrectable error status register fields. Table 14-64.
PAGE 793
PCI Express Interface Controller Table 14-65 describes the PCI Express uncorrectable error mask register fields. Table 14-65. PCI Express Uncorrectable Error Mask Register Fields Description Bits Name 31–21 — 20 UREM 19 ECRCEM 18 MTLPM Malformed TLP mask 17 RXOM Receiver overflow mask 16 UCM Unexpected completion mask 15 CAM Completer abort mask 14 CTOM 13 FCPEM Flow control protocol error mask 12 PTLPM Poisoned TLP mask 11–5 — 4 DLPEM 3–1 — 0 TEM 14.4.5.
PAGE 794
PCI Express Interface Controller Table 14-66 describes the PCI Express uncorrectable error severity register fields. Table 14-66.
PAGE 795
PCI Express Interface Controller Table 14-67 describes the PCI Express correctable error status register fields. Table 14-67. PCI Express Correctable Error Status Register Fields Description Bits Name 31–13 — 12 RTTO 11–9 — 8 RNR 7 BDLLP 6 BTLP 5–1 — 0 RXE 14.4.5.
PAGE 796
PCI Express Interface Controller Table 14-68. PCI Express Correctable Error Mask Register Fields Description (continued) Bits Name 5–1 — 0 RXEM 14.4.5.7 Description Reserved Receiver error mask PCI Express Advanced Error Capabilities and Control Register The PCI Express advanced error capabilities and control register is shown in Figure 14-72.
PAGE 797
PCI Express Interface Controller Offset 0x11C Access: Read-only 31 24 23 R Byte 0 16 15 Byte 1 8 7 Byte 2 0 Byte 3 W Reset Offset All zeros 0x120 Access: Read-only 31 24 23 R Byte 4 16 15 Byte 5 8 7 Byte 6 0 Byte 7 W Reset Offset All zeros 0x124 Access: Read-only 31 24 23 R Byte 8 16 15 Byte 9 8 7 Byte A 0 Byte B W Reset Offset All zeros 0x128 Access: Read-only 31 24 23 R Byte C 16 15 Byte D 8 7 Byte E 0 Byte F W Reset All zeros Figure 14-73.
PAGE 798
PCI Express Interface Controller 14.4.5.9 PCI Express Root Error Command Register The PCI Express root error command register is shown in Figure 14-74. Offset 0x12C Access: Read/Write 31 16 R — W Reset All zeros 15 3 R — W Reset 2 1 0 FERE NFERE CERE All zeros Figure 14-74. PCI Express Root Error Command Register Table 14-71 describes the PCI Express root error command register fields. Table 14-71.
PAGE 799
PCI Express Interface Controller Table 14-72 describes the PCI Express root error command register fields. Table 14-72. PCI Express Root Error Status Register Fields Description Bits Name 31–27 AEIMN 26–7 — 6 FEMR 5 NFEMR 4 FUF 3 Description Advanced error interrupt message number. Reserved Fatal error messages received. Non-fatal error messages received. First uncorrectable fatal. MEFNFR Multiple ERR_FATAL/NONFATAL received. 2 EFNFR ERR_FATAL/NONFATAL received.
PAGE 800
PCI Express Interface Controller 14.4.6 PCI Express Controller Internal Control and Status Registers (CSRs) This section describes the PCI Express controller internal control and status registers. 14.4.6.1 PCI Express LTSSM State Status Register (PEX_LTSSM_STAT) PEX_LTSSM_STAT, shown in Figure 14-77, provides details on link training status. This register is useful for debugging link training failures. Offset 0x404 Access: Read-only 31 7 R 6 — 0 Status Code W Reset All zeros Figure 14-77.
PAGE 801
PCI Express Interface Controller Table 14-75.
PAGE 802
PCI Express Interface Controller the Rx link of PHY. At a given time, either N_FTS or N_FTS_COM value is used based on the setting of common clock configuration bit in the configuration space. Offset 0x41C Access: R/W 31 16 15 R 8 — W Reset 0 0 0 0 0 0 0 0 7 0 N_FTS_COM 0 0 0 0 0 0 0 0 0 1 0 0 0 0 N_FTS 0 0 0 1 0 0 0 0 0 0 Figure 14-78. PCI Express N_FTS Control Register The fields of the PCI Express N_FTS Control Register are described in Table 14-76. Table 14-76.
PAGE 803
PCI Express Interface Controller Table 14-77 describes PCI Express N_FTS control register fields. Table 14-77. PCI Express ACK Replay Timeout Register Fields Description Bits Name 31–27 — 26–13 ACKRTV Description Reserved Ack Replay Timeout Value. Timeout value to wait for reception of ACK DLLP from the link side by the DLL before re-transmitting TLPs. The protocol specifies this value in symbol times for various combinations of max-payload size and negotiated link width.
PAGE 804
PCI Express Interface Controller Offset 0x440 Access: Mixed 31 6 R 5 0 — W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKRN 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Figure 14-80. PCI Express Core Clock Ratio Register (PEX_GCLK_RATIO) Table 14-78 describes the PEX_GCLK_RATIO fields. Table 14-78. PEX_GCLK_RATIO Fields Description Bits Name 31–6 — 5–0 CLKRN 14.4.6.5 Description Reserved Clock Ratio Numerator.
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PCI Express Interface Controller 14.4.6.6 PCI Express PME Time-Out Register (PEX_PME_TIMEOUT) (EP Mode Only) PEX_PME_TIMEOUT, shown in Figure 14-82, is used to program the time-out value that the controller uses before re-sending a PME message to the host. If PME is requested by a function and the host does not clear the associated PME_STAT bit even after this time-out has expired, the PME message is sent again to the host by the PCI Express controller. This register is supported only for EP mode.
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PCI Express Interface Controller Table 14-81 describes the PCI Express ASPM request timer register fields. Table 14-81. PCI Express ASPM Request Timer Register Fields Description Bits Name 31–13 — 12–0 ASPML1TMR 14.4.6.8 Description Reserved ASPM L1 request timer value. This is the time-out interval after sending NAK message, before a new ASPM L1 request from a downstream device is treated as a new ASPM L1 entry request.
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PCI Express Interface Controller Offset 0x47C Access: R/W 31 14 R — W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 12 11 PIP AIP APB 0 0 0 9 L1AL 0 0 8 6 5 4 3 2 L0SAL 0 0 0 0 0 MPLS 0 0 0 0 0 0 Figure 14-85. PCI Express Device Capabilities Update Register The fields of the PCI Express Device Capabilities Update Register are described in Table 14-83. Table 14-83.
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PCI Express Interface Controller upstream device. This register has to be programmed before setting the config-ready bit in the PCI Express configuration ready register so that the host reads the correct information during enumeration. Offset 0x480 Access: R/W 31 14 13 R — W Reset 0 0 0 0 0 0 0 0 0 11 10 L1EXL 0 0 0 0 0 0 0 0 0 1 1 1 8 7 6 L0SEXL ASPM 1 0 0 1 1 5 0 MLW 0 0 0 0 0 1 Figure 14-86.
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PCI Express Interface Controller 14.4.6.11 PCI Express Slot Capabilities Update Register (PEX_SLCAP_UPDATE) The PCI Express slot capabilities update register shown in Figure 14-87 is used to set the values to the PCI Express slot capabilities register in the PCI Express configuration header (offset 0x60). It can be used when the device is configured as an End Point to make the correct slot information available to the upstream device.
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PCI Express Interface Controller external host reads the correct capability advertisements during enumeration, the CFG_READY bit in this register should be set only after all relevant configuration registers are programmed. Offset 0x4B0 Access: Mixed 31 1 R — W Reset 0 CFG_READY All zeros Figure 14-88. PCI Express Configuration Ready Register (PEX_CFG_READY) The fields of the PCI Express configuration ready register are described in Table 14-86. Table 14-86.
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PCI Express Interface Controller Offset 0x4D8 Access: Mixed 31 12 11 R 0 MASK W Reset 1 1 1 1 1 1 0 0 0 0 0 — 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 14-89. PCI Express BAR Size Low Configuration Register (PEX_BAR_SIZEL) The fields of the PEX_BAR_SIZEL register are described in Table 14-87. Table 14-87. PEX_BAR_SIZEL Fields Description Bits Name Description 31–12 MASK Mask. Sets the mask for the BAR, and any bit with a value of zero is masked.
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PCI Express Interface Controller The fields of the PEX_BAR_SEL register are described in Table 14-88. Table 14-88. PEX_BAR_SEL Fields Description Bits Name 31–2 — 1–0 SEL 14.4.7.3 Description Reserved. Must be zeros. Select. Selects the specific BAR size to be programmed by the PEX_BAR_SIZEL and PEX_BAR_SIZEH registers. 00 PEX_BAR_SIZEL points to BAR0 in address 0x010 (Window 0, 32 bit address). 01 PEX_BAR_SIZEL points to BAR1 in address 0x014 (Window 1, 32 bit address).
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PCI Express Interface Controller Offset 0x590 (RC mode only) Access: Mixed 31 22 21 R 0 — PME_TO_ACK_TIMEOUT W Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 1 0 1 0 0 0 1 1 0 0 0 0 0 Figure 14-92. PCI Express PME_To_Ack Timeout Register (PEX_PME_TO_ACK_TOR) The fields of the PEX_PME_TO_ACK_TOR are described in Table 14-90. Table 14-90.
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PCI Express Interface Controller Table 14-91. PEX_PME_TO_ACK_SR Fields Description (continued) Bits Name Description 1 L2L3RDY Entered L2/L3 ready state. This bit is set by hardware when the current power management state is L2/L3 Ready. 100nsec after this bit is set, it is safe for the Power manager to switch off the power of the downstream device. Once set, this bit will remain set, till software clears it by writing 1’b1 to this bit. 0 PTACKMR PME_To_Ack message received.
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PCI Express Interface Controller Read DMA engines, a message manager and a set of configuration registers. Note that programming errors may result in undefined behavior. 14.5.1 PCI Express CSB Bridge Configuration Space The PCI Express CSB Bridge contains configuration registers for controlling and monitoring the PCI Express and CSB related operations.
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PCI Express Interface Controller 14.5.2.1 PCI Express CSB Bridge Control Register (PEX_CSB_CTRL) PEX_CSB_CTRL, shown in Figure 14-95, controls the operation of the PCI Express to CSB bridge. Offset 0x808 Access: Read/Write 31 16 R — W Reset 0 0 0 0 0 15 R 0 0 0 10 9 8 7 — W Reset 0 0 0 0 0 DSAD 0 0 0 0 1 0 0 0 0 0 0 4 3 2 1 0 — 0 0 RDMAE WDMAE IBPIOE OBPIOE 1 1 0 0 0 0 Figure 14-95.
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PCI Express Interface Controller 14.5.2.2 PCI Express DMA Descriptor Timer Register (PEX_DMA_DSTMR) PEX_DMA_DSTMR, shown in Figure 14-96, contains the timer value the DMA engine should wait for before reading the next descriptor once it encounters a descriptor that is not ready. The timer should be programmed to allow sufficient number of clocks before the DMA tries to fetch the descriptors again. Offset 0x814 Access: Read/Write 31 0 R DSRT W Reset All zeros Figure 14-96.
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PCI Express Interface Controller Table 14-95 defines the bit field for PEX_CSB_STAT. Table 14-95. PEX_CSB_STAT Register Fields Description Bits Name 31–25 — 24 RDMARP 23–17 — 16 WDMARP 15–9 — 8 IBPIORP 7–1 — 0 OBPIORP 14.5.3 Description Reserved Read DMA read transaction pending. Indicates whether a response is pending from the PCI Express bus to a transfer by the read DMA engine. 0 No response pending 1 Response is pending Reserved Write DMA read transaction pending.
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PCI Express Interface Controller Table 14-96 defines the bit fields for PEX_CSB_OBCTRL. Table 14-96. PEX_CSB_OBCTRL Register Fields Description Bits Name 31–10 — Reserved 9–7 TC Traffic class. Indicates TC value to be used for TLP generation corresponding to traffic received by the CSB slave. 6–4 — Reserved 3 CFGWE Configuration window enable. Must be set to enable an outbound configuration transaction.
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PCI Express Interface Controller Table 14-97. PEX_CSB_OBSTAT Register Fields Description (continued) Bit Name Description 2 CSBER CSB Bridge error. Hardware sets this bit to indicate that an error has occurred during a PIO outbound access to the CSB bridge by a CSB master. 1 BMPER Bridge mapping error. Hardware sets this bit to indicate that an outbound PIO operation could not be completed successfully because a CSB bridge address mapping error has occurred. 0 BENER Bridge enable error.
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PCI Express Interface Controller 14.5.4.2 PCI Express Inbound PIO Status Register (PEX_CSB_IBSTAT) PEX_CSB_IBSTAT, shown in Figure 14-101, maintains the status of PCI Express Inbound PIO operations through the PCI Express CSB bridge. Offset 0x8E4 Access: w1c 31 16 R — W Reset All zeros 15 3 R — W Reset 2 1 0 CSBER BRGER BENER w1c w1c w1c All zeros Figure 14-101. PCI Express Inbound PIO Status Register (PEX_CSB_IBSTAT) Table 14-99 defines the bit fields for PEX_CSB_IBSTAT.
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PCI Express Interface Controller 14.5.5.1 PCI Express Write DMA Control Register (PEX_WDMA_CTRL) PEX_WDMA_CTRL, shown in Figure 14-102, controls the WDMA operations. Offset 0x9A0 Access: Read/Write 31 16 R — W Reset All zeros 15 11 R — W Reset 10 9 SNOOP RLXO 8 5 4 2 TC 1 0 SUS START All zeros Figure 14-102. PCI Express Write DMA Control Register (PEX_WDMA_CTRL) Table 14-100 defines the bit fields of PEX_WDMA_CTRL. Table 14-100.
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PCI Express Interface Controller Table 14-101 defines the bit fields of PEX_WDMA_ADDR. Table 14-101. PEX_WDMA_ADDR Register Fields Description Bit Name Description 31–0 FDSA First descriptor address. Indicates the address of the first descriptor on the CSB local memory (byte-swapped). 14.5.5.3 PCI Express Write DMA Status Register (PEX_WDMA_STAT) PEX_WDMA_STAT, shown in Figure 14-104, maintains the status of write DMA operations.
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PCI Express Interface Controller 14.5.5.4 PCI Express Read DMA Control Register (PEX_RDMA_CTRL) PEX_RDMA_CTRL, shown in Figure 14-105, controls the RDMA operations. Offset 0xA40 Access: Read/Write 31 16 R — W Reset All zeros 15 11 R — W 10 9 8 2 SNOOP RLXO Reset — 1 0 SUS START All zeros Figure 14-105. PCI Express Read DMA Control Register (PEX_RDMA_CTRL) Table 14-103 defines the bit fields of PEX_RDMA_CTRL. Table 14-103.
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PCI Express Interface Controller Table 14-104 defines the bit fields of PEX_RDMA_ADDR. Table 14-104. PEX_RDMA_ADDR Register Fields Description Bits Name 31–0 FDSA First descriptor address. Indicates the address of the first descriptor on the CSB local memory (byte swapped). 14.5.5.6 Description PCI Express Read DMA Status Register (PEX_RDMA_STAT) PEX_RDMA_STAT, shown in Figure 14-107, maintains the status of read DMA operations.
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PCI Express Interface Controller 14.5.6 Mailbox Registers This section describes the following registers: • Section 14.5.6.1, “PCI Express Outbound Mailbox Control Register (PEX_OMBCR)” • Section 14.5.6.2, “PCI Express Outbound Mailbox Data Register (PEX_OMBDR)” • Section 14.5.6.3, “PCI Express Inbound Mailbox Control Register (PEX_IMBCR)” • Section 14.5.6.4, “PCI Express Inbound Mailbox Data Register (PEX_IMBDR)” 14.5.6.
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PCI Express Interface Controller Table 14-107. PEX_OMBDR Register Fields Description Bits Name 31–0 MBD 14.5.6.3 Description Mailbox Data. Contains the data to be read by the PCI Express host upon receiving an interrupt. PCI Express Inbound Mailbox Control Register (PEX_IMBCR) PEX_IMBCR, shown in Figure 14-110, controls the generation of an interrupt to the local host indicating that the PCI Express host has programmed the data mailbox register, and it is ready to be read.
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PCI Express Interface Controller 14.5.7 PCI Express Host Interrupt Registers This section describes the registers for generating interrupts to the PCI Express host. It consists of interrupt status registers and enable registers. Interrupts are generated only if the corresponding enable bit is set. The device supports generation of MSI interrupts. Using these registers to generate interrupts to the PCI Express host is applicable for only PCI Express EP applications. 14.5.7.
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PCI Express Interface Controller Table 14-110. PEX_HIER Register Fields Description (continued) Bits Name 3 IPAIE Inbound PIO transaction aborted interrupt enable. If set, enables the generation of an interrupt for every inbound PCI Express PIO transaction aborted. 2 IPCIE Inbound PIO transaction completed interrupt enable. If set, enables the generation of an interrupt for every inbound PCI Express PIO transaction that successfully completes.
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PCI Express Interface Controller Table 14-111. PEX_HISR Register Fields Description (continued) Bits Name 4 WDC WDMA chain descriptor transfer completed. Hardware sets this bit when a write DMA transaction for the last descriptor in a chain descriptor successfully completes. 3 IPA Inbound PIO transaction aborted. Hardware sets this bit when an inbound PCI Express PIO transaction aborts. 2 IPC Inbound PIO transaction completed.
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PCI Express Interface Controller Offset 0xBC0 Access: Read/Write 31 5 R 4 — W Reset 0 IVEC All zeros Figure 14-115. PCI Express Host Inbound PIO Interrupt Vector Register (PEX_HIPIVR) Table 14-113 defines the bit fields of PEX_HIPIVR. Table 14-113. PEX_HIPIVR Register Fields Description Bits Name 31–5 — 4–0 IVEC 14.5.7.5 Description Reserved Interrupt vector. Contains the vector value for MSI.
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PCI Express Interface Controller Table 14-115 defines the bit fields of PEX_HRDIVR. Table 14-115. PEX_HRDIVR Register Fields Description Bit Name 31–5 — 4–0 IVEC 14.5.7.7 Description Reserved Interrupt Vector. Contains the vector value for MSI. PCI Express Host Miscellaneous Interrupt Vector Register (PEX_HMIVR) PEX_HMIVR, shown in Figure 14-118, contains the interrupt vector for mailbox message for MSI interrupts issued to the PCI Express host. This includes CSB bridge reset and mailbox message.
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PCI Express Interface Controller Offset 0xBE0 Access: Read/Write 31 25 R — W 24 23 17 IPAIE Reset — 16 IPCIE All zeros 15 9 R — W Reset 8 7 1 OPAIE — 0 OPCIE All zeros Figure 14-119. CSB System PIO Interrupt Enable Register (PEX_CSPIER) Table 14-117 defines the bit fields of PEX_CSPIER. Table 14-117. PEX_CSPIER Register Fields Description Bit Name 31–25 — 24 IPAIE 23–17 — 16 IPCIE 15–9 — 8 OPAIE 7–1 — 0 OPCIE 14.5.8.
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PCI Express Interface Controller Offset 0xBE4 Access: Read/Write 31 17 R — W Reset 16 WDAIE All zeros 15 9 R — W 8 7 1 WDSIE Reset — 0 WDCIE All zeros Figure 14-120. CSB System Write DMA Interrupt Enable Register (PEX_CSWDIER) Table 14-118 defines the bit fields of PEX_CSWDIER. Table 14-118. PEX_CSWDIER Register Fields Description Bit Name 31–17 — 16 WDAIE 15–9 — 8 WDSIE 7–1 — 0 WDCIE 14.5.8.3 Description Reserved WDMA transfer aborted interrupt enable.
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PCI Express Interface Controller Table 14-119 defines the bit fields of PEX_CSRDIER. Table 14-119. PEX_CSRDIER Register Fields Description Bit Name 31–17 — 16 RDAIE 15–9 — 8 RDSIE 7–1 — 0 RDCIE 14.5.8.4 Description Reserved RDMA transfer aborted interrupt enable. If set, enables the generation of interrupt for every Read DMA transaction aborted. Reserved. RDMA descriptor transfer completed interrupt enable.
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PCI Express Interface Controller Table 14-120. PEX_CSMIER Register Fields Description (continued) Bit Name Description 17 PMETOIE PME to Ack timeout event interrupt enable. If set, enables the generation of an interrupt when a PME to Ack timeout occurs. This bit is valid only in RC mode. 16 — 15 ROFIE 14 ECRCIE ECRC error interrupt enable. If set, enables the generation of an interrupt when a TLP is received by PCI Express and it fails ECRC check. 13 PTLPIE Poisoned TLP interrupt enable.
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PCI Express Interface Controller 14.5.8.5 CSB System PIO Interrupt Status Register (PEX_CSPISR) PEX_CSPISR, shown in Figure 14-123, maintains the status for interrupts issued to the CSB system host related to PIO operation. Offset 0xBF0 Access: w1c 31 25 R — W 24 23 17 IPA — w1c Reset 16 IPC w1c All zeros 15 9 R — W 8 1 OPA — w1c Reset 0 OPC w1c All zeros Figure 14-123.
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PCI Express Interface Controller 14.5.8.6 CSB System Write DMA Interrupt Status Register (PEX_CSWDISR) PEX_CSWDISR, shown in Figure 14-124, maintains the status for interrupts issued to the CSB host related to WDMA operation. Offset 0xBF4 Access: w1c 31 17 R — W Reset 16 WDA w1c All zeros 15 9 R — W 8 7 WDS 0 WDC — w1c Reset 1 w1c All zeros Figure 14-124. CSB System Write DMA Interrupt Status Register (PEX_CSWDISR) Table 14-122 defines the bit fields of PEX_CSWDISR.
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PCI Express Interface Controller Table 14-123 defines the bit fields of PEX_CSRDISR. Table 14-123. PEX_CSRDISR Register Fields Description Bits Name 31–17 — 16 RDA 15–9 — 8 RDS 7–1 — 0 RDC 14.5.8.8 Description Reserved RDMA transfer aborted. Indicates that a Read DMA transaction was aborted. Reserved RDMA descriptor transfer completed. Indicates that a read DMA transaction corresponding to a descriptor successfully completed. Reserved RDMA chain descriptor transfer completed.
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PCI Express Interface Controller Table 14-124. PEX_CSMISR Register Fields Description (continued) Bits Name Description 20 PSCH Power state change. Indicates that a device power state change occurred. Change in Device power state (D state) for function-0. D-state can transition between the supported values of D0, D1, D2 and D3-hot. PM software changes D-state with a configuration write to PMCSR register in PM capability of the PCI Express.
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PCI Express Interface Controller 14.5.9 PCI Express Power Management Registers This section describes the PCI Express power management control register. 14.5.9.1 PCI Express Power Management Control Register (PEX_PM_CTRL) This PCI Express PM Control Register shown in Figure 14-127, is used to control the link power management by the PCI Express controller.
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PCI Express Interface Controller Table 14-125. PEX_PM_CTRL Register Fields Description (continued) Bits 1 Name Description PMETO Send PME Turn off message. This bit is valid only in RC mode and instructs the PCI Express controller to send PME_Turn_Off message to downstream devices. After setting this bit, the user must not try to transmit TLPs or initiate PME requests as the power may be switched off. This field is Write only. Read always returns zero. 0 IL2L3 Initiate L2/L3 entry.
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PCI Express Interface Controller Table 14-126. PEX_OWAR0–PEX_OWAR3 Register Fields Description (continued) Bits Name Description 7–5 TC 4 NSNP No snoop enable. When this bit and the PCI Express device control register [Enable No Snoop] bit are set, the No Snoop bit for the packet is enabled. This attribute is not applicable and must be cleared for configuration requests, I/O requests, and memory requests that are Message Signaled Interrupts.
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PCI Express Interface Controller Table 14-127 defines the bit fields of the PEX_OWBAR0–PEX_OWBAR3. Table 14-127. PEX_OWBARn Register Fields Description Bits Name Description 31–12 BA Base address. The CSB window base address. Represents the CSB-based address for the window. The actual address is a concatenation of the BAR field as most significant bits and 12 zeroes as least significant bits {BA[31–12], 0x000}. 11–0 — Reserved. Must be zeros. 14.5.10.
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PCI Express Interface Controller PEX_OWTARLn and PEX_OWTARHn registers. This register should be used in 64-bit addressing. Otherwise it should contain all zeroes. Offset 0xCAC, 0xCBC, 0xCCC, 0xCDC Access: Read/Write 31 0 R TAH W Reset All zeros Figure 14-131. PCI Express Outbound Window Translation Address Register High n (PEX_OWTARH0–PEX_OWTARH3) Table 14-129 defines the bit fields of PEX_OWTARHn. Table 14-129.
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PCI Express Interface Controller 14.5.11.1 PCI Express EP Inbound Window Translation Address Register n (PEX_EPIWTAR0–PEX_EPIWTAR3) PEX_EPIWTAR0–PEX_EPIWTAR3, shown in Figure 14-132, contain the CSB address to be mapped for a PCI Express inbound transaction hitting the respective BAR window. Inbound and outbound windows for the same bus should not overlap.
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PCI Express Interface Controller 14.5.12.1 PCI Express RC Inbound Window Attributes Register n (PEX_RCIWAR0 –PEX_RCIWAR3) PEX_RCIWAR0–PEX_RCIWAR3, shown in Figure 14-133, controls the mapping of a PCI Express inbound PIO transaction to a CSB transaction. This register is valid only in RC mode. Offset 0xE60, 0xE70, 0xE80, 0xE90 31 28 R Access: Read/Write 27 16 — W SIZE Reset All zeros 15 12 R 11 SIZE W 5 — Reset 4 3 NSNP NSOV 2 1 TYPE 0 EN All zeros Figure 14-133.
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PCI Express Interface Controller 14.5.12.2 PCI Express RC Inbound Window Translation Address Register n (PEX_RCIWTAR0–PEX_RCIWTAR3) PEX_RCIWTAR0–PEX_RCIWTAR3), shown in Figure 14-134, contain the CSB address to be mapped for a PCI Express inbound transaction hitting the respective base address register of this window. These registers are valid only in RC mode. Inbound and outbound windows for the same bus should not overlap.
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PCI Express Interface Controller Table 14-134 defines the bit fields of PEX_RCIWBARLn. Table 14-134. PEX_RCIWBARLn Register Fields Description Bits Name Description 31–12 BAL Base address low. Lower portion of the PCI Express address base. Represents the PCI Express-based address for the window. The actual address is a concatenation of the BAL field as most significant bits and 12 zeroes as least significant bits {BAL[31–12], 0x000}. 11–0 — Reserved. Must be zeros. 14.5.12.
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PCI Express Interface Controller Each PCI Express device is divided into two halves, transmit (Tx) and receive (Rx), and each of these halves is further divided into three layers—transaction, data link, and physical—as shown in Figure 14-138. Transaction Transaction Data Link Data Link Physical Physical Logical Sub-Block Logical Sub-Block Electrical Sub-Block Electrical Sub-Block RX TX RX TX Figure 14-138.
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PCI Express Interface Controller • • • Section 14.6.1.8, “I/O Space Addressing” Section 14.6.1.9, “Configuration Space Access” Section 14.6.1.10, “Inbound Messages” 14.6.1.1 Address Translation Windows (ATMUs) The device includes four general purpose inbound and outbound address translation windows which are used to map between the PCI Express domain and the CSB domain (referred as local address space).
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PCI Express Interface Controller Table 14-136.
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PCI Express Interface Controller Table 14-137. PCI Express Transactions (continued) PCI Express Transaction MPC8378E/MPC8377E Support as an Initiator MPC8378E/MPC8377E Support as a Target Definition CplD Yes Yes Completion with Data CplLk No No Completion for Locked Memory Read without Data CplDLk No No Completion for Locked Memory Read with Data 14.6.1.
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PCI Express Interface Controller Note that it is possible for one outbound configuration transaction to bypass another outbound configuration transaction due to CRS status and the ability for hardware to retry the transaction. 14.6.1.7 Memory Space Addressing A PCI Express memory transaction can address a 32- or 64-bit memory space. The Fmt[0] field in the PCI Express header for a 32-bit address packet is 0 while a 64-bit address packet has a 1 indication.
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PCI Express Interface Controller As RC the PCI Express controller configuration access mechanism utilizes a memory-mapped address space to access device configuration registers. To achieve this, software can program the TYPE field of the PEX_OWARn register to 0x0 in one of the outbound ATMU windows to perform a configuration access.
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PCI Express Interface Controller Table 14-138. Configuration Address Mapping (continued) CSB Address Bits Numbering PCI Express Address Bits Numbering 30–31 1–0 PCI Express Configuration Space Reserved Note: It is the user’s responsibility to set the reserved bit fields to zero (especially bits 15–12). Note: The configuration cycle generation mechanism does not differentiate from internal or external configuration cycle.
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PCI Express Interface Controller Sixteen buses mean that the bus number can range from 0x00 to 0x0F. In general, if there are 2n bus numbers to be configured, n number of address bits are needed to represent the variation of bus number ranging from 0 to 2n – 1.
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PCI Express Interface Controller on the PCI Express link with Bus Number = 1, Device Number = 0, Function Number = 0, and Register Number = 0. Similarly, if the software intends to read the above EP’s configuration space offset 0x440, it can generate a CSB-based memory transaction to address 0x5100_0440. Once the transaction hitting the above configured outbound window, the ATMU translates it into a transaction with PCI Express address 0x0100_0440.
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PCI Express Interface Controller Table 14-139 lists the messages and the actions that take place in RC mode. Table 14-139.
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PCI Express Interface Controller Table 14-140 lists the messages and the actions that take place in EP mode. Table 14-140.
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PCI Express Interface Controller 14.6.2.1 EP Interrupt Generation Hardware MSI generation is supported for the interrupt events described in Section 14.5.7, “PCI Express Host Interrupt Registers.” 14.6.2.1.
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PCI Express Interface Controller 14.6.2.1.2 Software MSI Generation Host software needs to set up the MSI capability registers to enable MSI mode and put the correct values for the MSI address and data register. Next, local software must read the MSI address in the MSI capability register and configure the outbound ATMU window to map the translated address to the MSI address.
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PCI Express Interface Controller a memory read from the mailbox data register and read the message. The following steps are required in order to use the outbound mailbox mechanism. 1. The RC should set the MSIE bit of the PCI Express MSI message control register (address 0x72 of the configuration space) to enable the generation of MSI. 2.
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PCI Express Interface Controller 5. The local host can read the message content from the PCI Express inbound mailbox data register (PEX_IMBDR). 6. The local host should clear PEX_IMBCR[READY] and all the interrupt event and status bits in the relevant registers. 7. The RC can repeat steps 3–4 after verifying that the PEX_IMBCR[READY] is cleared. 14.6.4 Power Management All device power states are supported except D3cold. In addition, all link power states are supported except the L2 and L3 states.
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PCI Express Interface Controller Figure 14-141 shows an example of how to generate WAKE#. Controller in EP mode WAKE# GPOUT[24] Figure 14-141. Example—How to Generate WAKE# 14.6.5 Hot Reset When a hot reset condition occurs, the controller (in both RC and EP mode) initiates a cleanup of all outstanding transactions and goes into suspend mode.
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PCI Express Interface Controller 4. Start the SerDes reset sequence by setting RST field (bit 0) in the SerDes reset control register (SRDSRSTCTL). See Section 15.3.6, “SerDesn Reset Control Register (SRDSRSTCTL).” 5. Poll RDONE field (bit 1) in the SerDes reset control register (SRDSRSTCTL). 6. After RDONE is set, wait at least 1 ms. 7. Program the PCI Express control registers 1 and 2. See Section 5.2.2.11, “PCI Express Control Registers (PECR1).
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PCI Express Interface Controller control registers. The hardware updates the status register on completion of a DMA data transfer for a descriptor and a chain of descriptors, and report errors.
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PCI Express Interface Controller Table 14-143. DMA Descriptor Bit Fields Description (continued) Bits Width Attribute Description 95–64 32 Control Source address. Software programs this field to indicate the source address. For a write DMA, the source address is the CSB address. For a read DMA, the source address is a CSB address that is mapped to a PCI Express memory address using the outbound window address translation. 63–37 27 — 36 1 Status PCI Express error.
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PCI Express Interface Controller When a response to a CSB read request is received, the segments are packed into the PCI Express memory write request according to the PCI Express MPS. All data requested by the DMA controller is processed as a single data stream as described in this section. For example, when a 256-byte request starting from address 0 is segmented to eight 32-byte CSB read requests, then it is segmented to two 128-byte PCI Express write requests (assuming a 128-byte MPS).
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PCI Express Interface Controller Any remaining data, if applicable from the last CSB address boundary to the PCI Express end address, is packed into the last segment. Each completion is segmented as a single data stream according to these rules. For example, when a 256-byte request starting from address 0 is converted to two 128-byte PCI Express read requests (assuming a 128-byte MPS/MRRS), the bridge issues two read requests if a tag and a completion buffer are available.
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PCI Express Interface Controller The number of ways, n, is software configurable. In this mode, n descriptors are written in contiguous memory locations. The implicit address of the next descriptor is the next memory location. The last descriptor in the contiguous block contains the explicit address pointer of the next set of n descriptors. Address 0x0 will never be part of the chain since it should close the chain. Non-contiguous valid descriptors are not supported.
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PCI Express Interface Controller 14.8.4.3 Descriptor Format For more information on descriptor format, refer to Section 14.8.1, “DMA Descriptor Format.” The fetched descriptors are stored in the bridge configuration space registers. Each time the DMA controller fetches a new set of descriptors, the register is updated to indicate the value/fields of the descriptors.
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Chapter 15 SerDes PHY 15.1 Introduction The SerDes PHY block includes the following components: • SerDes PHY • Protocol multiplexer and converter per protocol • Control registers and control logic • Power-down/reset state machine for cold (power-on) or warm (software-initiated) reset of the SerDes, PCVTR, and controllers • Interface with the clock controls 15.1.
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SerDes PHY 15.1.3 Mode of Operation The SerDes PHY block supports one lane (Lane A) running 1 PCI Express at 2.5 Gbps as the mode of operation. NOTE SerDes block’s second lane, Lane B, is externally not available and therefore, should be powered down. For more information, see Section 15.3.2, “SerDes Control Register 1 (SRDSCR1).” 15.1.4 Clock The SerDes control has one clock which is running at platform speed. This is an internally generated clock based off of the system clock. 15.
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SerDes PHY Table 15-1. SerDes External Signals—Detailed Signal Descriptions (continued) Signal I/O RXA I Description Serial receiver data, lane A, positive. Timing Assertion/Negation—Serial differential receiver input which can be configured to meet the PCI Express specifications. I RXA Serial receiver data, lane A, complement. Timing Assertion/Negation—Serial differential receiver input which can be configured to meet the PCI Express specifications.
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SerDes PHY 15.3.1 SerDes Control Register 0 (SRDSCR0) SRDSCR0, shown in Figure 15-2, contains the functional control bits for the SerDes logic. Offset 0x000 Access: Read/write 0 1 2 3 TLCCA — RXEQA 0 0 0 16 17 4 15 R — W Reset 1 0 19 20 0 0 1 0 0 0 0 23 24 25 26 27 SDPD — IACCA 0 0 1 0 0 0 0 29 30 31 RXEIA — 0 0 R DPPA TXEQA — — W Reset 1 1 0 0 1 1 0 0 1 0 0 Figure 15-2.
PAGE 877
SerDes PHY Table 15-3. SRDSCR0 Field Descriptions (continued) 1 Bits Name Description 17–19 TXEQA 20–23 — 24 SDPD 25 — 26 IACCA 27–29 — 30 RXEIA 31 — Sets the peak value for output swing of transmitters and the amount of transmit equalization for lane A. Transmit equalization selection bus for lane A. 000 No equalization 001 1.09 relative amplitude 010 1.2 relative amplitude 011 1.33 relative amplitude 100 1.5 relative amplitude 101 1.71 relative amplitude 110 2.
PAGE 878
SerDes PHY 15.3.2 SerDes Control Register 1 (SRDSCR1) SRDSCR1, shown in Figure 15-3, contains the functional control bits for the SerDes logic. Lane A can be powered down using SRDSCR1[0]. The entire SerDes must be reset to activate a lane from power-down. Refer to Section 15.3.6, “SerDesn Reset Control Register (SRDSRSTCTL).
PAGE 879
SerDes PHY Table 15-4. SRDSCR1 Field Descriptions (continued) Bits Name Description 27 SDRST Master reset for SerDes logic. Resets all logic in SerDes lane A. Software needs to set and clear this bit. 0 Application mode 1 Reset Note: SDRST can also be done by setting SRDSnRSTCTL[RST]. In this case, SDRST can self-clear. 28–29 — 30 RPTA 31 — 15.3.3 Reserved To enable repeater mode on lane A.
PAGE 880
SerDes PHY Table 15-5. SRDSCR2 Field Descriptions (continued) Bits Name 22–23 PEICA 24–31 — 15.3.4 Description PCII-EXP Receiver electrical idle detection control 00 Exit from idle ~85 UI and unexpected idle detect ~1 s (application mode) 01 Exit from idle ~85 UI and unexpected idle detect ~10 s 10 Exit from idle ~45 UI and unexpected idle detect ~1 s 11 Bypass Reserved SerDes Control Register 3 (SRDSCR3) SRDSCR3, shown in Figure 15-5, contains the functional control bits for the SerDes logic.
PAGE 881
SerDes PHY 15.3.5 SerDes Control Register 4 (SRDSCR4) SRDSCR4, shown in Figure 15-6, contains the functional control bits for the SerDes logic. NOTE To power down lane A, use SRDSCR1[0] (refer to Section 15.3.2, “SerDes Control Register 1 (SRDSCR1)”). The valid combination for protocol select is PCI Express mode (PROTA = 001), which is only an 1 lane. The reference clock can be either 100 or 125 MHz.
PAGE 882
SerDes PHY 15.3.6 SerDesn Reset Control Register (SRDSRSTCTL) SRDSRSTCTL, shown in Figure 15-7, contains the control for SerDes reset state machine counter values. Offset 0x20 0 R W Reset RST 0 Access: Read/write 1 2 RDONE 0 3 4 — 0 6 7 15 PSCL 0 0 0 — 0 0 0 1 0 0 0 1 0 16 31 R — W Reset 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 Figure 15-7. SerDes Reset Control Register (SRDSRSTCTL) Table 15-8 describes the SRDSRSTCTL register. Table 15-8.
PAGE 883
SerDes PHY • SRDSCR4 register — Configure protocol select, reference clock frequency, and PCI Express 1 lane (refer to Figure 15-6) Valid combination for protocol select is: • PCI Express mode (AD_PROTO_SEL/EH_PROTO_SEL[2–0] = 001) is only an 1 lane. The reference clock can be either 100 or 125 MHz. • • 15.5 NOTE The entire SerDes need to be reset in order to activate lane A from power-down. The SRDSCR4 register is initialized base on RCWH[TSEC1M] and RCWH[TSEC2M].
PAGE 884
SerDes PHY • The unused lane B of SerDes may be powered down by programming PDB bit in SRDSCR1 to 1. For more information, see Section 15.3.2, “SerDes Control Register 1 (SRDSCR1).” Powering down the SerDes includes the following steps: 1. Disable the PLL and place its output clocks into a known, static state. 2. Power down the receiver termination and amplifier cells. In PCI Express mode, there is still a differential termination, but its value is no longer calibrated.
PAGE 885
Chapter 16 Enhanced Three-Speed Ethernet Controllers 16.1 Overview The enhanced three-speed Ethernet controllers (eTSECs) of the device interface to 10 Mbps, 100 Mbps, and 1 Gbps Ethernet/IEEE 802.3™ networks. For Ethernet, an external PHY or SerDes device is required to complete the interface to the media. Each eTSEC supports multiple standard media-independent interfaces. Two eTSECs are available, providing flexible options for connectivity and control access at different speeds.
PAGE 886
Enhanced Three-Speed Ethernet Controllers 1588 Timer Clock 1588 Timer Regs Host Interface Controller Tx BDC Rx BDC Register Access Control Rx FIFO 2 Kbytes Tx FIFO Control Rx FIFO Control Register Array Ethernet Address Filter Tx FIFO 10 Kbytes Tx Queue Scheduler TCP/IP Checksum Rx Filing Engine Ethernet/ IP/TCP/UDP Parser RMON MAC Layer GMII Reduced Pin I/F Clocks To PHY MII To PHY MII Mgmt RGMII Figure 16-1. eTSEC Block Diagram 16.
PAGE 887
Enhanced Three-Speed Ethernet Controllers — — — — — • • • • IP v4 and IP v6 header recognition on receive IP v4 header checksum verification and generation TCP and UDP checksum verification and generation Per-packet configurable off-load Recognition of VLAN, stacked-VLAN, 802.
PAGE 888
Enhanced Three-Speed Ethernet Controllers • • • 16.
PAGE 889
Enhanced Three-Speed Ethernet Controllers • • • • • • • 16.4 controlled by software using the serial management interface (MDC/MDIO signals) to the transceiver. Clause 22.2.4 of the IEEE 802.3 specification describes the MII management interface. MAC address recognition options The options supported are promiscuous, broadcast, exact unicast address match, exact unicast virtual address match to support router redundancy, and multicast hash match. For detailed descriptions refer to Section 16.6.2.
PAGE 890
Enhanced Three-Speed Ethernet Controllers Each eTSEC network interface supports multiple options: • The MII option requires 18 I/O signals (including the MDIO and MDC MII management interface) and supports both a data and a management interface to the PHY (transceiver) device. The MII option supports both 10- and 100-Mbps Ethernet rates. • The RGMII option is reduced-pin implementations of the GMII. • 1588 timer signals. Table 16-1 lists the network interface signals. Table 16-1.
PAGE 891
Enhanced Three-Speed Ethernet Controllers Table 16-1. eTSECn Network Interface Signal Properties (continued) Reset State Signal Name Function TSEC_TMR_TRIG2 1588—Trigger in 2 External timer trigger input 2. This is an asynchronous general purpose input (chip external input pin). — TSEC_TMR_PP1 1588—Pulse out 1 Timer pulse per period 1. It is phase aligned with 1588 timer clock (chip external output pin). 0 TSEC_TMR_PP2 1588—Pulse out 2 Timer pulse per period 2.
PAGE 892
Enhanced Three-Speed Ethernet Controllers Table 16-2. eTSEC Signals—Detailed Signal Descriptions (continued) Signal I/O Description TSECn_GTX_CLK O Gigabit transmit clock. This signal is an output from the eTSEC into the PHY. In RGMII mode, TSECn_GTX_CLK becomes the transmit clock and provides timing reference during 1000Base-T (125 MHz), 100Base-T (25 MHz) and 10Base-T (2.5 MHz) transmissions.
PAGE 893
Enhanced Three-Speed Ethernet Controllers Table 16-2. eTSEC Signals—Detailed Signal Descriptions (continued) Signal I/O Description TSECn_TXD[3:0] O Transmit data out. DVIn MII mode, TSECn_TXD[3:0] represent a nibble of data to be sent from the MAC to the PHY when TSECn_TX_EN is asserted and have no meaning while TSECn_TX_EN is negated. In RGMII mode, data bits 3:0 are transmitted on the rising edge of TSECn_GTX_CLK, and data bits 7:4 are transmitted on the falling edge of TSECn_GTX_CLK.
PAGE 894
Enhanced Three-Speed Ethernet Controllers descriptors are used to pass data buffers and related buffer status or frame information between the hardware and software. All accesses to and from the registers must be made as 32-bit accesses. There is no support for accesses of sizes other than 32 bits. Writes to reserved register bits must always store 0, as writing 1 to reserved bits may have unintended side-effects. Reads from unmapped register addresses return zero.
PAGE 895
Enhanced Three-Speed Ethernet Controllers In this table and in the register figures and field descriptions, the following access definitions apply: • Reserved fields are always ignored for the purposes of determining access type. • R/W, R, and W (read/write, read only, and write only) indicate that all the non-reserved fields in a register have the same access type. • w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them.
PAGE 896
Enhanced Three-Speed Ethernet Controllers Table 16-4.
PAGE 897
Enhanced Three-Speed Ethernet Controllers Table 16-4. Module Memory Map (continued) eTSEC1 Offset Name1 Access 2 Reset Section/Page — — — 0x2_4280 TMR_TXTS1_ID* - Tx time stamp identification (set 1) R/W 0x0000_0000 16.5.3.2.10/16-45 0x2_4284 TMR_TXTS2_ID* - Tx time stamp identification (set 2) R/W 0x0000_0000 16.5.3.2.10/16-45 — — — 0x2_42C0 TMR_TXTS1_H* - Tx time stamp high (set 1) R/W 0x0000_0000 16.5.3.2.
PAGE 898
Enhanced Three-Speed Ethernet Controllers Table 16-4. Module Memory Map (continued) eTSEC1 Offset Name1 Access 2 Reset Section/Page R/W 0x0000_0000 16.5.3.3.10/16-60 — — — R/W 0x0000_0000 16.5.3.3.10/16-60 — — — R/W 0x0000_0000 16.5.3.3.10/16-60 — — — R/W 0x0000_0000 16.5.3.3.10/16-60 — — — R/W 0x0000_0000 16.5.3.3.11/16-60 — — — R/W 0x0000_0000 16.5.3.3.11/16-60 — — — R/W 0x0000_0000 16.5.3.3.11/16-60 — — — R/W 0x0000_0000 16.5.3.3.
PAGE 899
Enhanced Three-Speed Ethernet Controllers Table 16-4. Module Memory Map (continued) eTSEC1 Offset Name1 Access 2 Reset Section/Page R/W 0x0000_0600 16.5.3.5.5/16-70 — — — 0x2_4520 MIIMCFG—MII management configuration R/W 0x0000_0007 16.5.3.5.6/16-70 0x2_4524 MIIMCOM—MII management command R/W 0x0000_0000 16.5.3.5.7/16-71 0x2_4528 MIIMADD—MII management address R/W 0x0000_0000 16.5.3.5.8/16-72 0x2_452C MIIMCON—MII management control W 0x0000_0000 16.5.3.5.
PAGE 900
Enhanced Three-Speed Ethernet Controllers Table 16-4. Module Memory Map (continued) eTSEC1 Offset Name1 Access 2 Reset Section/Page 0x2_4570 MAC06ADDR1*—MAC exact match address 6, part 1 R/W 0x0000_0000 0x2_4574 MAC06ADDR2*—MAC exact match address 6, part 2 R/W 0x0000_0000 16.5.3.5.15/16-75 16.5.3.5.
PAGE 901
Enhanced Three-Speed Ethernet Controllers Table 16-4. Module Memory Map (continued) eTSEC1 Offset Name1 Access 2 Reset Section/Page 0x2_46AC RBCA—Receive broadcast packet counter R/W 0x0000_0000 16.5.3.6.12/16-83 0x2_46B0 RXCF—Receive control frame packet counter R/W 0x0000_0000 16.5.3.6.13/16-83 0x2_46B4 RXPF—Receive PAUSE frame packet counter R/W 0x0000_0000 16.5.3.6.14/16-84 0x2_46B8 RXUO—Receive unknown OP code counter R/W 0x0000_0000 16.5.3.6.
PAGE 902
Enhanced Three-Speed Ethernet Controllers Table 16-4. Module Memory Map (continued) eTSEC1 Offset Name1 Access 2 Reset Section/Page eTSEC Counter Control and TOE Statistics Registers 0x2_4730 CAR1—Carry register one register3 w1c 0x0000_0000 16.5.3.6.44/16-99 3 w1c 0x0000_0000 16.5.3.6.45/16-100 0x2_4738 CAM1—Carry register one mask register R/W 0xFE03_FFFF 16.5.3.6.46/16-101 0x2_473C CAM2—Carry register two mask register R/W 0x000F_FFFD 16.5.3.6.
PAGE 903
Enhanced Three-Speed Ethernet Controllers Table 16-4. Module Memory Map (continued) eTSEC1 Offset Name1 Access 2 Reset Section/Page 16.5.3.9.
PAGE 904
Enhanced Three-Speed Ethernet Controllers Table 16-4. Module Memory Map (continued) eTSEC1 Offset Name1 Access 2 Reset Section/Page 0x2_4E14 TMR_STAT* - time stamp status register R/W 0x0000_0000 16.5.3.10.6/16-115 0x2_4E18 TMR_CNT_H* - timer counter high register R/W 0x0000_0000 16.5.3.10.7/16-115 0x2_4E1C TMR_CNT_L* - timer counter low register R/W 0x0000_0000 16.5.3.10.7/16-115 0x2_4E20 TMR_ADD* - Timer drift compensation addend register R/W 0x0000_0000 16.5.3.10.
PAGE 905
Enhanced Three-Speed Ethernet Controllers 16.5.3 Memory-Mapped Register Descriptions This section provides a detailed description of all the eTSEC registers. Because all of the eTSEC registers are 32 bits wide, only 32-bit register accesses are supported. 16.5.3.1 eTSEC General Control and Status Registers This section describes general control and status registers used for both transmitting and receiving Ethernet frames. All of the registers are 32 bits wide. 16.5.3.1.
PAGE 906
Enhanced Three-Speed Ethernet Controllers 16.5.3.1.2 Controller ID Register (TSEC_ID2) The controller ID register (TSEC_ID2) is a read-only register. The TSEC_ID2 register is used to identify the eTSEC block configuration. Offset eTSEC1:0x2_4004; eTSEC2:0x2_5004 0 9 R 10 Reset 0 0 0 0 0 15 16 23 24 TSEC_INT — W Access: Read only 0 0 0 0 0 1 1 0 0 0 31 TSEC_CFG — 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 Figure 16-3.
PAGE 907
Enhanced Three-Speed Ethernet Controllers Each eTSEC can issue three kinds of hardware interrupt to the PIC: 1. Transmit data frame interrupts—Issued whenever bits TXB or TXF of IEVENT are set to 1 and either transmit interrupt coalescing is disabled or the interrupt coalescing thresholds have been met for TXF. To negate this hardware interrupt, software must clear both TXB and TXF bits. 2.
PAGE 908
Enhanced Three-Speed Ethernet Controllers Table 16-8 describes the fields of the IEVENT register. Table 16-8. IEVENT Field Descriptions Bits Name 0 BABR 1 RXC Receive control interrupt. A control frame was received while MACCFG1[Rx_Flow] is set. As soon as the transmitter finishes sending the current frame, a pause operation is performed. 0 Control frame not received. 1 Control frame received. 2 BSY Busy condition interrupt.
PAGE 909
Enhanced Three-Speed Ethernet Controllers Table 16-8. IEVENT Field Descriptions (continued) Bits Name Description 11 TXF Transmit frame interrupt. This bit indicates that a frame was transmitted and that the last corresponding transmit buffer descriptor (TxBD) was updated. This only occurs if the I (interrupt) bit in the status word of the buffer descriptor is set. The specific transmit queue that was updated has its TXF bit set in TSTAT. 0 No frame transmitted/TxBD not updated.
PAGE 910
Enhanced Three-Speed Ethernet Controllers Table 16-8. IEVENT Field Descriptions (continued) Bits Name Description 27 FGPI Filer generated general purpose interrupt on a set of filer rule match. This bit will be set upon reception of a frame that matches a GPI rule sequence that is specified in the filer. It is synchronized with the setting of RXF. 0 No filer generated interrupt has occurred. 1 The filer has accepted a frame via a matching rule that the RQFCR[GPI] bit set.
PAGE 911
Enhanced Three-Speed Ethernet Controllers Figure 16-5 describes the IMASK register.
PAGE 912
Enhanced Three-Speed Ethernet Controllers Table 16-9.
PAGE 913
Enhanced Three-Speed Ethernet Controllers Table 16-10 describes the fields of the EDIS register. Table 16-10. EDIS Field Descriptions Bits Name 0–1 — 2 BSYDIS 3 Description Reserved Busy disable. 0 Allow eTSEC to report IEVENT[BSY] status and halt buffer descriptor queue if BSY condition occurs. 1 Do not set IEVENT[BSY] and do not halt buffer descriptor queue if BSY condition occurs. EBERRDIS Ethernet controller bus error disable.
PAGE 914
Enhanced Three-Speed Ethernet Controllers Table 16-10. EDIS Field Descriptions (continued) Bits Name 30 DPEDIS 31 PERRDIS 16.5.3.1.6 Description Data parity error disable. 0 Allow eTSEC to report IEVENT[DPE] status. 1 Do not set IEVENT[DPE] if a parity error occurs in eTSEC’s FIFO or filer arrays. Receive frame parse error disable. 0 Allow eTSEC to report IEVENT[PERR] status. 1 Do not set IEVENT[PERR] if a parse error occurs on a received frame.
PAGE 915
Enhanced Three-Speed Ethernet Controllers Table 16-11. ECNTRL Field Descriptions (continued) Bits Name Description 19 STEN MIB counter statistics enabled. 0 Statistics not enabled 1 Enables internal counters to update This is a steady state signal and must be set prior to enabling the Ethernet controller and must not be changed without proper care. 20–24 — 25 GMIIM 26 — 27 RPM 28 R100M 29–31 — Reserved GMII interface mode.
PAGE 916
Enhanced Three-Speed Ethernet Controllers Offset eTSEC1:0x2_4028; eTSEC2:0x2_5028 Access: Read/Write 0 15 16 R 31 PTE W PT Reset All zeros Figure 16-8. PTV Register Definition Table 16-13 describes the fields of the PTV register. Table 16-13. PTV Field Descriptions Bits Name Description 0–15 PTE Extended pause control. This field allows software to add a 16-bit additional control parameter into the PAUSE frame to be sent when TCTRL[TFC_PAUSE] is set. Note that current IEEE 802.
PAGE 917
Enhanced Three-Speed Ethernet Controllers Table 16-14. DMACTRL Field Descriptions (continued) Bits 25 Name Description TBDSEN TxBD snoop enable. 0 Disables snooping of all transmit BD memory accesses. 1 Enables snooping of all transmit BD memory accesses. 26 — 27 GRS Graceful receive stop. If this bit is set, the Ethernet controller stops receiving frames following completion of the frame currently being received. (That is, after a valid end of frame was received).
PAGE 918
Enhanced Three-Speed Ethernet Controllers Offset eTSEC1:0x2_4030; eTSEC2:0x2_5030 Access: Mixed 0 26 R 31 — W TBIPA Reset All zeros Figure 16-10. TBIPA Register Definition Table 16-15 describes the fields of the TBIPA register. Table 16-15. TBIPA Field Descriptions Bits Name 0–26 — 27–31 TBIPA 16.5.3.2 Description Reserved This field holds the PHY address of the MII management interface. Note: The value of 0 is reserved. External PHY cannot have the address 0.
PAGE 919
Enhanced Three-Speed Ethernet Controllers Table 16-16. TCTRL Field Descriptions (continued) Bits Name Description 18 TUCSEN TCP/UDP header checksum generation enable. When set, the eTSEC offloads TCP or UDP header checksum generation. See Section 16.6.3.2, “Transmit Path Off-Load and Tx PTP Packet Parsing.” 0 TCP or UDP header checksum generation is disabled even if enabled in a transmit frame control block.
PAGE 920
Enhanced Three-Speed Ethernet Controllers 16.5.3.2.2 Transmit Status Register (TSTAT) This register is read/write-one-to-clear and is written by the eTSEC to convey DMA status information for each TxBD ring. The halt bit only has meaning for enabled rings. After processing transmit-related interrupts, software should use TSTAT to restart transmission from rings that may have been affected by the interrupt condition.
PAGE 921
Enhanced Three-Speed Ethernet Controllers Table 16-17 describes the fields of the TSTAT register. Table 16-17. TSTAT Field Descriptions Bits 0 Name Description THLT0 Transmit halt of ring 0. Set by the eTSEC if is no longer processing transmit frames from this TxBD ring, and DMA from this ring is disabled. To re-start transmission from this TxBD ring, this bit must be cleared by writing 1 to it.
PAGE 922
Enhanced Three-Speed Ethernet Controllers Table 16-17. TSTAT Field Descriptions (continued) Bits 3 Name Description THLT3 Transmit halt of ring 3. Set by the eTSEC if is no longer processing transmit frames from this TxBD ring, and DMA from this ring is disabled. To re-start transmission from this TxBD ring, this bit must be cleared by writing 1 to it. This bit is set only on a general error condition (as in IEVENT[TXE]), regardless of TQUEUE[EN3], or if no ready TxBDs can be fetched.
PAGE 923
Enhanced Three-Speed Ethernet Controllers Table 16-17. TSTAT Field Descriptions (continued) Bits 6 Name Description THLT6 Transmit halt of ring 6. Set by the eTSEC if is no longer processing transmit frames from this TxBD ring, and DMA from this ring is disabled. To re-start transmission from this TxBD ring, this bit must be cleared by writing 1 to it. This bit is set only on a general error condition (as in IEVENT[TXE]), regardless of TQUEUE[EN6], or if no ready TxBDs can be fetched.
PAGE 924
Enhanced Three-Speed Ethernet Controllers Table 16-17. TSTAT Field Descriptions (continued) Bits Name 23 Description TXF7 Transmit frame event occurred on ring 7. Set by the eTSEC if IEVENT[TXF] was set in relation to transmitting a frame from this ring. 24–31 — 16.5.3.2.
PAGE 925
Enhanced Three-Speed Ethernet Controllers 16.5.3.2.4 Transmit Interrupt Coalescing Register (TXIC) The TXIC register enables and configures the operational parameters for interrupt coalescing associated with transmitted frames. Figure 16-14 describes the definition for the TXIC register. Offset eTSEC1:0x2_4110; eTSEC2:0x2_5110 0 R W 1 2 3 ICEN ICCS — Reset Access: Read/Write 10 11 ICFT 15 16 — 31 ICTT All zeros Figure 16-14.
PAGE 926
Enhanced Three-Speed Ethernet Controllers 16.5.3.2.5 Transmit Queue Control Register (TQUEUE) The TQUEUE register, shown in Figure 16-15, selectively enables each of the TxBD rings 0–7. By default, TxBD ring 0 is enabled. Offset eTSEC1:0x2_4114; eTSEC2:0x2_5114 0 Access: Read/Write 15 R — W 16 17 18 19 20 21 22 23 24 EN0 EN1 EN2 EN3 EN4 EN5 EN6 EN7 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 31 — 0 0 0 0 0 0 0 0 Figure 16-15.
PAGE 927
Enhanced Three-Speed Ethernet Controllers TR03WT has no effect. A description of how queue weights affect eTSEC’s round-robin algorithm appears in Section 16.6.4.3.2, “Modified Weighted Round-Robin Queuing (MWRR).” Figure 16-16 describes the TR03WT register. Offset eTSEC1:0x2_4140; eTSEC2:0x2_5140 0 R W 7 Access: Read/Write 8 WT0 15 16 WT1 Reset 23 24 WT2 31 WT3 All zeros Figure 16-16. TR03WT Register Definition Table 16-21 describes the fields of the TR03WT register. Table 16-21.
PAGE 928
Enhanced Three-Speed Ethernet Controllers Table 16-22 describes the fields of the TR47WT register. Table 16-22. TR47WT Field Descriptions Bits Name 0–7 WT4 Weighting value for TxBD ring 4 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a minimum of WT4  64 bytes of data are scheduled for transmission from TxBD ring 4. Clearing this field prevents transmission. 8–15 WT5 Weighting value for TxBD ring 5 when TCTRL[TXSCHED] = 10.
PAGE 929
Enhanced Three-Speed Ethernet Controllers 16.5.3.2.9 Transmit Descriptor Base Address Registers (TBASE0–TBASE7) The TBASEn registers are written by the user with the base address of each TxBD ring n. Each such value must be divisible by eight, since the three least significant bits always write as 000. Figure 16-19 describes the definition for the TBASEn registers. Offset eTSEC1:0x2_4204+8n; eTSEC2:0x2_5204+8n Access: Read/Write 0 28 29 R TBASEn W Reset 31 — All zeros Figure 16-19.
PAGE 930
Enhanced Three-Speed Ethernet Controllers 16.5.3.2.11 Transmit Time Stamp Register (TMR_TXTS1–2_H/L) Transmit stamp register (TMR_TXTSn_H/L). This register holds the value of the TMR_CNT_H/L when a frame tagged for timestamp capture (via Tx FCB[PTP]) is transmitted. Upon transmission of the start of frame symbol of such a frame, the value in TMR_CNT_H/L is copied into TMR_TXTSn_H/L. This register is read only in normal operation. Figure 16-21 depicts TMR_TXTSn_H/L.
PAGE 931
Enhanced Three-Speed Ethernet Controllers Table 16-27 describes the fields of the RCTRL register. Table 16-27. RCTRL Field Descriptions Bits Name Description 0–6 — Reserved 7 TS Time stamp incoming packets as padding bytes. PAL field is set to 8 if the PAL field is programmed to less than 8. Must be set to zero if TMR_CTRL[TE]=0. 8–10 — Reserved 11–15 PAL 16 — 17 LFC Lossless flow control.
PAGE 932
Enhanced Three-Speed Ethernet Controllers Table 16-27. RCTRL Field Descriptions (continued) Bits Name 22 IPCSEN 23 TUCSEN TCP or UDP Checksum verification enable. See Section 16.6.3.3, “Receive Path Off-Load.” 0 TCP or UDP checksums are not verified by the eTSEC—even if layer 4 parsing is enabled. 1 Perform TCP or UDP checksum verification if PRSDEP = 11. 24–25 Description IP Checksum verification enable. See Section 16.6.3.3, “Receive Path Off-Load.
PAGE 933
Enhanced Three-Speed Ethernet Controllers Writing 1 to any bit of this register clears it. Software should clear the QHLT bit to take eTSEC’s receiver function out of halt state for the associated queue. Figure 16-23 describes the definition for the RSTAT register.
PAGE 934
Enhanced Three-Speed Ethernet Controllers Table 16-28. RSTAT Field Descriptions (continued) Bits Name Description 13 QHLT5 RxBD queue 5 is halted. It is a hardware-initiated stop indication. (DMACTRL[GRS] being set by the user does not cause a QHLT5 to be set.). The current frame and all other frames directed to a halted queue are discarded. A write with a value of 1 re-enables the queue for receiving. 0 This queue is enabled for reception.
PAGE 935
Enhanced Three-Speed Ethernet Controllers Table 16-29 describes the fields of the RXIC register. Table 16-29. RXIC Field Descriptions Bits Name Description 0 ICEN Interrupt coalescing enable 0 Interrupt coalescing is disabled. Interrupts are raised as they are received. 1 Interrupt coalescing is enabled.
PAGE 936
Enhanced Three-Speed Ethernet Controllers Table 16-30. RQUEUE Field Descriptions (continued) Bits Name 16–23 — 24–31 ENn Description Reserved Receive queue n enable. 0 RxBD ring is not queried for reception. In effect the receive queue is disabled. 1 RxBD ring is queried for reception. 16.5.3.3.
PAGE 937
Enhanced Three-Speed Ethernet Controllers Table 16-31. RBIFX Field Descriptions (continued) Bits Name Description 8–9 B1CTL Location of byte 1 of property ARB. 00 Byte 1 is not extracted, and appears as zero in property ARB. 01 Byte 1 is located in the received frame at offset (B1OFFSET – 8) bytes from the first byte of the Ethernet DA. In non-FIFO modes, a negative effective offset points to bytes of the standard Ethernet preamble. Values of B1OFFSET less than 8 are reserved in FIFO modes.
PAGE 938
Enhanced Three-Speed Ethernet Controllers Offset eTSEC1:0x2_4334; eTSEC2:0x2_5334 Access: Read/Write 0 23 24 R 31 — W Reset RQFAR All zeros Figure 16-27. Receive Queue Filer Table Address Register Definition Table 16-32 describes the fields of the RQFAR register. Table 16-32. RQFAR Field Descriptions Bits Name 0–23 — 24–31 Description Reserved RQFAR Current index of receive queue filer table, which spans a total of 256 entries. 16.5.3.3.
PAGE 939
Enhanced Three-Speed Ethernet Controllers Table 16-33. RQFCR Field Descriptions (continued) Bit Name Description 22 CLE Cluster entry/exit (used in combination with AND bit). This bit brackets clusters, marking the start and end entries of a cluster. Clusters cannot be nested. 0 Regular RQCTRL entry. 1 If entry matches and AND = 1, treat subsequent entries as belonging to a nested cluster and enter the cluster; otherwise skip all entries up to and including the next cluster exit.
PAGE 940
Enhanced Three-Speed Ethernet Controllers Offset eTSEC1:0x2_433C; eTSEC2:0x2_533C Access: Read/Write 0 15 R — W Reset R W All zeros 16 17 18 19 20 21 22 23 24 25 26 27 EBC VLN CFI JUM IPF — IP4 IP6 ICC ICV TCP UDP Reset 28 29 — 30 31 PER EER All zeros Figure 16-30. Receive Queue Filer Table Property ID1 Register Definition Table 16-34 describes the fields of the RQFPR register. \ Table 16-34.
PAGE 941
Enhanced Three-Speed Ethernet Controllers Table 16-34. RQFPR Field Descriptions (continued) PID1 Bit Name 0010 0–7 ARB 0011 0100 0101 0110 Description User-defined arbitrary bit field property: byte 0 extracted. Defaults to 0x00. 8–15 User-defined arbitrary bit field property: byte 1 extracted. Defaults to 0x00. 16–23 User-defined arbitrary bit field property: byte 2 extracted. Defaults to 0x00. 24–31 User-defined arbitrary bit field property: byte 3 extracted. Defaults to 0x00.
PAGE 942
Enhanced Three-Speed Ethernet Controllers Table 16-34. RQFPR Field Descriptions (continued) PID1 Bit Name 0111 0–15 — 16–31 ETY 0–19 — 20–31 VID 0–28 — 29–31 PRI 0–23 — 24–31 TOS 1000 1001 1010 Description Reserved, should be written with zero. Ethertype of next layer protocol, that is, last ethertype if layer 2 headers nest. Defaults to 0xFFFF.
PAGE 943
Enhanced Three-Speed Ethernet Controllers Table 16-34. RQFPR Field Descriptions (continued) PID1 Bit Name 1011 0–23 — 24–31 L4P Layer 4 protocol identifier as per published IANA specification. This is the last recognized protocol type recognized in the case of IPv6 extension headers. This value defaults to 0xFF to indicate that no layer 4 header was recognized (possibly due to absence of an IP header). 1100 0–31 DIA Destination IP address.
PAGE 944
Enhanced Three-Speed Ethernet Controllers 16.5.3.3.10 Receive Buffer Descriptor Pointers 0–7 (RBPTR0–RBPTR7) RBPTR0–RBPTR7 each contains the low-order 32 bits of the next receive buffer descriptor address for their respective RxBD ring. Figure 16-32 describes the RBPTR registers. These registers takes on the value of their ring’s associated RBASE when the RBASE register is written by software. Software must not write RBPTRn while eTSEC is actively receiving frames.
PAGE 945
Enhanced Three-Speed Ethernet Controllers Table 16-37 describes the fields of the RBASEn registers. Table 16-37. RBASE0–RBASE7 Field Descriptions Bits Name 0–28 Description RBASEn Receive base for ring n. RBASE defines the starting location in the memory map for the eTSEC RxBDs. This field must be 8-byte aligned. Together with setting the W (wrap) bit in the last BD, the user can select how many BDs to allocate for the receive packets.
PAGE 946
Enhanced Three-Speed Ethernet Controllers programmable register set, the pad/CRC behavior can be dynamically adjusted on a per-packet basis. 16.5.3.4.2 Controlling CSMA/CD The half-duplex register (HAFDUP) allows control over the carrier-sense multiple access/collision detection (CSMA/CD) logic of the eTSEC. Half-duplex mode is only supported for 10- and 100-Mbps operation.
PAGE 947
Enhanced Three-Speed Ethernet Controllers 16.5.3.4.4 Controlling Packet Flow Packet flow can be dealt with in a number of ways within eTSEC. A default retransmit attempt limit of 15 can be reduced using the half-duplex register. The slot time or collision window can be used to gate the retry window and possibly reduce the amount of transmit buffering within the system. The slot time for 10/100 Mbps is 512 bit times.
PAGE 948
Enhanced Three-Speed Ethernet Controllers Yet another parameter that can be modified through the MII registers is the length of the MII management interface preamble. After establishing that a PHY supports preamble suppression, the host may so configure the eTSEC. While enabled, the length of MII management frames are reduced from 64 clocks to 32 clocks. This effectively doubles the efficiency of the interface. 16.5.3.5 MAC Registers This section describes the MAC registers. 16.5.3.5.
PAGE 949
Enhanced Three-Speed Ethernet Controllers Table 16-39. MACCFG1 Field Descriptions (continued) Bits 15 Name Description Reset Tx Fun Reset transmit function block. This bit is cleared by default. 0 Normal operation. 1 Place the transmit function in reset. This block performs the frame transmission protocol. 16–22 — 23 Loop Back 24–25 — 26 Rx_Flow Receive flow. This bit is cleared by default. Must be 0 if MACCFG2[Full Duplex] = 0. 0 The receive MAC control ignores PAUSE flow control frames.
PAGE 950
Enhanced Three-Speed Ethernet Controllers 16.5.3.5.2 MAC Configuration 2 Register (MACCFG2) The MACCFG2 register is written by the user. Figure 16-36 describes the definition for the MACCFG2 register.
PAGE 951
Enhanced Three-Speed Ethernet Controllers Table 16-40. MACCFG2 Field Descriptions (continued) Bits Name Description 26 Huge Frame Huge frame enable. This bit is cleared by default. 0 Limit the length of frames received to less than or equal to the maximum frame length value (MAXFRM[Maximum Frame]) and limit the length of frames transmitted to less than the maximum frame length. See Section 16.6.7, “Buffer Descriptors,” for further details of buffer descriptor bit updating.
PAGE 952
Enhanced Three-Speed Ethernet Controllers 16.5.3.5.3 Inter-Packet Gap/Inter-Frame Gap Register (IPGIFG) The IPGIFG register is written by the user. Figure 16-37 describes the definition for IPGIFG.
PAGE 953
Enhanced Three-Speed Ethernet Controllers 16.5.3.5.4 Half-Duplex Register (HAFDUP) The HAFDUP register is written by the user. Figure 16-38 describes the HAFDUP register.
PAGE 954
Enhanced Three-Speed Ethernet Controllers 16.5.3.5.5 Maximum Frame Length Register (MAXFRM) The MAXFRM register is written by the user. Figure 16-39 shows the MAXFRM register. Offset eTSEC1:0x2_4510; eTSEC2:0x2_5510 Access: Read/Write 0 15 16 R 31 — W Reset 0 0 0 0 0 0 0 0 Maximum Frame 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 Figure 16-39. Maximum Frame Length Register Definition Table 16-43 describes the fields of the MAXFRM register. Table 16-43.
PAGE 955
Enhanced Three-Speed Ethernet Controllers Table 16-44. MIIMCFG Field Descriptions (continued) Bits Name Description 27 No Pre Preamble suppress. This bit is cleared by default. 0 The MII MGMT performs Mgmt read/write cycles with 32 clocks of preamble. 1 The MII MGMT suppresses preamble generation and reduces the Mgmt cycle from 64 clocks to 32 clocks. This is in accordance with IEEE 802.3/22.2.4.4.2. 28 — 29–31 MgmtClk 16.5.3.5.
PAGE 956
Enhanced Three-Speed Ethernet Controllers 16.5.3.5.8 MII Management Address Register (MIIMADD) The MIIMADD register is written by the user. Figure 16-42 shows the MIIMADD register. Offset eTSEC1:0x2_4528 Access: Read/Write 0 18 19 R — W Reset 23 24 PHY Address 26 27 — 31 Register Address All zeros Figure 16-42. MIIMADD Register Definition Table 16-46 describes the fields of the MIIMADD register. Table 16-46.
PAGE 957
Enhanced Three-Speed Ethernet Controllers 16.5.3.5.10 MII Management Status Register (MIIMSTAT) The MIIMSTAT register is read only by the user. Figure 16-44 describes the definition for the MIIMSTAT register. O Offset eTSEC1:0x2_4530 Access: Read only 0 15 16 R PHY Status — W 31 Reset All zeros Figure 16-44. MIIMSTAT Register Definition Table 16-48 describes the fields of the MIIMSTAT register. Table 16-48.
PAGE 958
Enhanced Three-Speed Ethernet Controllers 16.5.3.5.12 Interface Status Register (IFSTAT) Figure 16-46 shows the IFSTAT register. Offset eTSEC1:0x2_453C; eTSEC2:0x2_553C Access: Read only 0 21 R — W 22 23 Excess Defer Reset 31 — All zeros Figure 16-46. Interface Status Register Definition Table 16-50 describes the fields of the FSTAT register. Table 16-50. IFSTAT Field Descriptions Bits Name 0–21 — 22 Description Reserved Excess Defer Excessive transmission defer.
PAGE 959
Enhanced Three-Speed Ethernet Controllers Table 16-51. MACSTNADDR1 Field Descriptions (continued) Bit Name Description 16–23 Station Address, 4th Octet This field holds the fourth octet of the station address. The fourth octet (station address bits 24–31) defaults to a value of 0x0. 24–31 Station Address, 3rd Octet This field holds the third octet of the station address. The third octet (station address bits 16–23) defaults to a value of 0x0. 16.5.3.5.
PAGE 960
Enhanced Three-Speed Ethernet Controllers For any valid, non-zero MAC address received, exact match registers can be excluded individually by clearing them to all zero bytes. Offset eTSEC1:0x2_4548+8n; eTSEC2:0x2_5548+8n 0 R 7 8 Exact Match Address, 6th Octet W Access: Read/Write 15 16 Exact Match Address, 5th Octet Reset 23 24 Exact Match Address, 4th Octet 31 Exact Match Address, 3rd Octet All zeros Figure 16-49.
PAGE 961
Enhanced Three-Speed Ethernet Controllers Table 16-54 describes the fields of a MACxADDR2 register. Table 16-54. MAC01ADDR2–MAC15ADDR2 Field Descriptions Bit Name Description 0–7 Exact Match Address, 2nd Octet This field holds the second octet of the exact match address. The second octet (destination address bits 8–15) defaults to a value of 0x0. 8–15 Exact Match Address, 1st Octet This field holds the first octet of the exact match address.
PAGE 962
Enhanced Three-Speed Ethernet Controllers 16.5.3.6.1 Transmit and Receive 64-Byte Frame Counter (TR64) Figure 16-51 describes the definition for the TR64 register. Offset eTSEC1:0x2_4680; eTSEC2:0x2_5680 0 R 9 Access: Read/Write 10 31 — W TR64 Reset All zeros Figure 16-51. Transmit and Receive 64-Byte Frame Register Definition Table 16-55 describes the fields of the TR64 register. Table 16-55.
PAGE 963
Enhanced Three-Speed Ethernet Controllers 16.5.3.6.3 Transmit and Receive 128- to 255-Byte Frame Counter (TR255) Figure 16-53 describes the definition for the TR255 register. Offset eTSEC1:0x2_4688; eTSEC2:0x2_5688 0 9 R Access: Read/Write 10 31 — W TR255 Reset All zeros Figure 16-53. Transmit and Received 128- to 255-Byte Frame Register Definition Table 16-57 describes the fields of the TR255 register. Table 16-57.
PAGE 964
Enhanced Three-Speed Ethernet Controllers 16.5.3.6.5 Transmit and Receive 512- to 1023-Byte Frame Counter (TR1K) Figure 16-55 shows the TR1K register. Offset eTSEC1:0x2_4690; eTSEC2:0x2_5690 0 9 R Access: Read/Write 10 31 — W TR1K Reset All zeros Figure 16-55. Transmit and Received 512- to 1023-Byte Frame Register Definition Table 16-59 describes the fields of the TR1K register. Table 16-59. TR1K Field Descriptions Bits Name 0–9 — 10–31 TR1K Description Reserved 16.5.3.6.
PAGE 965
Enhanced Three-Speed Ethernet Controllers 16.5.3.6.7 Transmit and Receive 1519- to 1522-Byte VLAN Frame Counter (TRMGV) Figure 16-57 describes the definition for the TRMGV register. Offset eTSEC1:0x2_4698; eTSEC2:0x2_5698 0 Access: Read/Write 9 R 10 31 — W TRMGV Reset All zeros Figure 16-57. Transmit and Received 1519- to 1522-Byte VLAN Frame Register Definition Table 16-61 describes the fields of the TRMGV register. Table 16-61.
PAGE 966
Enhanced Three-Speed Ethernet Controllers Table 16-63 describes the fields of the RPKT register. Table 16-63. RPKT Field Descriptions Bits Name 0–9 — 10-31 RPKT Description Reserved Receive packet counter. Increments for each frame received packet (including bad packets, all unicast, broadcast, and multicast packets). 16.5.3.6.10 Receive FCS Error Counter (RFCS) Figure 16-60 describes the definition for the RFCS register.
PAGE 967
Enhanced Three-Speed Ethernet Controllers 16.5.3.6.12 Receive Broadcast Packet Counter (RBCA) Figure 16-62 describes the definition for the RBCA register. Offset eTSEC1:0x2_46AC; eTSEC2:0x2_56AC 0 9 R Access: Read/Write 10 31 — W RBCA Reset All zeros Figure 16-62. Receive Broadcast Packet Counter Register Definition Table 16-66 describes the fields of the RBCA register. Table 16-66. RBCA Field Descriptions Bits Name 0–9 — 10–31 RBCA Description Reserved Receive broadcast packet counter.
PAGE 968
Enhanced Three-Speed Ethernet Controllers 16.5.3.6.14 Receive Pause Frame Packet Counter (RXPF) Figure 16-64 describes the definition for the RXPF register. Offset eTSEC1:0x2_46B4; eTSEC2:0x2_56B4 Access: Read/Write 0 15 16 R — W 31 RXPF Reset All zeros Figure 16-64. Receive Pause Frame Packet Counter Register Definition Table 16-68 describes the fields of the RXPF register. Table 16-68.
PAGE 969
Enhanced Three-Speed Ethernet Controllers 16.5.3.6.16 Receive Alignment Error Counter (RALN) Figure 16-66 describes the definition for the RALN register. Offset eTSEC1:0x2_46BC; eTSEC2:0x2_56BC Access: Read/Write 0 15 16 R — W 31 RALN Reset All zeros Figure 16-66. Receive Alignment Error Counter Register Definition Table 16-70 describes the fields of the RALN register. Table 16-70. RALN Field Descriptions Bits Name 0–15 — 16–31 RALN Description Reserved Receive alignment error counter.
PAGE 970
Enhanced Three-Speed Ethernet Controllers 16.5.3.6.18 Receive Code Error Counter (RCDE) Figure 16-68 describes the definition for the RCDE register. Offset eTSEC1:0x2_46C4; eTSEC2:0x2_56C4 Access: Read/Write 0 15 16 R — W 31 RCDE Reset All zeros Figure 16-68. Receive Code Error Counter Register Definition Table 16-72 describes the fields of the RCDE register. Table 16-72. RCDE Field Descriptions Bits Name 0–15 — 16–31 Description Reserved RCDE Receive code error counter.
PAGE 971
Enhanced Three-Speed Ethernet Controllers 16.5.3.6.20 Receive Undersize Packet Counter (RUND) Figure 16-70 describes the definition for the RUND register. Offset eTSEC1:0x2_46CC; eTSEC2:0x2_56CC Access: Read/Write 0 15 16 R — W 31 RUND Reset All zeros Figure 16-70. Receive Undersize Packet Counter Register Definition Table 16-74 describes the fields of the RUND register. Table 16-74. RUND Field Descriptions Bits Name 0–15 — 16–31 RUND Description Reserved Receive undersize packet counter.
PAGE 972
Enhanced Three-Speed Ethernet Controllers 16.5.3.6.22 Receive Fragments Counter (RFRG) Figure 16-72 describes the definition for the RFRG register. Offset eTSEC1:0x2_46D4; eTSEC2:0x2_56D4 Access: Read/Write 0 15 16 R — W 31 RFRG Reset All zeros Figure 16-72. Receive Fragments Counter Register Definition Table 16-76 describes the fields of the RFRG register. Table 16-76. RFRG Field Descriptions Bits Name 0–15 — 16–31 RFRG Description Reserved Receive fragments counter.
PAGE 973
Enhanced Three-Speed Ethernet Controllers 16.5.3.6.24 Receive Dropped Packet Counter (RDRP) Figure 16-74 describes the definition for the RDRP register. Offset eTSEC1:0x2_46DC; eTSEC2:0x2_56DC Access: Read/Write 0 15 16 R — W 31 RDRP Reset All zeros Figure 16-74. Receive Dropped Packet Counter Register Definition Table 16-78 describes the fields of the RDRP register. Table 16-78. RDRP Field Descriptions Bits Name 0–15 — 16–31 RDRP Description Reserved Receive dropped packets counter.
PAGE 974
Enhanced Three-Speed Ethernet Controllers 16.5.3.6.26 Transmit Packet Counter (TPKT) Figure 16-76 describes the definition for the TPKT register. Offset eTSEC1:0x2_46E4; eTSEC2:0x2_56E4 0 9 R Access: Read/Write 10 31 — W TPKT Reset All zeros Figure 16-76. Transmit Packet Counter Register Definition Table 16-80 describes the fields of the TPKT register. Table 16-80. TPKT Field Descriptions Bits Name 0–9 — Description Reserved 10–31 TPKT Transmit packet counter.
PAGE 975
Enhanced Three-Speed Ethernet Controllers 16.5.3.6.28 Transmit Broadcast Packet Counter (TBCA) Figure 16-78 describes the definition for the TBCA register. Offset eTSEC1:0x2_46EC; eTSEC2:0x2_56EC 0 9 R Access: Read/Write 10 31 — W TBCA Reset All zeros Figure 16-78. Transmit Broadcast Packet Counter Register Definition Table 16-82 describes the fields of the TBCA register. Table 16-82.
PAGE 976
Enhanced Three-Speed Ethernet Controllers 16.5.3.6.30 Transmit Deferral Packet Counter (TDFR) Figure 16-80 describes the definition for the TDFR register. Offset eTSEC1:0x2_46F4; eTSEC2:0x2_56F4 Access: Read/Write 0 19 20 R — W Reset 31 TDFR All zeros Figure 16-80. Transmit Deferral Packet Counter Register Definition Table 16-84 describes the fields of the TDFR register. Table 16-84. TDFR Field Descriptions Bits Name 0–19 — 20–31 TDFR Description Reserved Transmit deferral packet counter.
PAGE 977
Enhanced Three-Speed Ethernet Controllers 16.5.3.6.32 Transmit Single Collision Packet Counter (TSCL) Figure 16-82 describes the definition for the TSCL register. Offset eTSEC1:0x2_46FC; eTSEC2:0x2_56FC Access: Read/Write 0 19 20 R — W Reset 31 TSCL All zeros Figure 16-82. Transmit Single Collision Packet Counter Register Definition Table 16-86 describes the fields of the TSCL register. Table 16-86.
PAGE 978
Enhanced Three-Speed Ethernet Controllers 16.5.3.6.34 Transmit Late Collision Packet Counter (TLCL) Figure 16-84 describes the definition for the TLCL register. Offset eTSEC1:0x2_4704; eTSEC2:0x2_5704 Access: Read/Write 0 19 20 R — W Reset 31 TLCL All zeros Figure 16-84. Transmit Late Collision Packet Counter Register Definition Table 16-88 describes the fields of the TLCL register. Table 16-88.
PAGE 979
Enhanced Three-Speed Ethernet Controllers 16.5.3.6.36 Transmit Total Collision Counter (TNCL) Figure 16-86 describes the definition for the TNCL register. Offset eTSEC1:0x2_470C; eTSEC2:0x2_570C Access: Read/Write 0 19 20 R 31 — W Reset TNCL All zeros Figure 16-86. Transmit Total Collision Counter Register Definition Table 16-90 describes the fields of the TNCL register. Table 16-90. TNCL Field Descriptions Bits Name 0–19 — 20–31 TNCL Description Reserved Transmit total collision counter.
PAGE 980
Enhanced Three-Speed Ethernet Controllers 16.5.3.6.38 Transmit Jabber Frame Counter (TJBR) Figure 16-88 describes the definition for the TJBR register. Offset eTSEC1:0x2_4718; eTSEC2:0x2_5718 Access: Read/Write 0 19 20 R 31 — W Reset TJBR All zeros Figure 16-88. Transmit Jabber Frame Counter Register Definition Table 16-92 describes the fields of the TJBR register. Table 16-92. TJBR Field Descriptions Bits Name 0–19 — 20–31 TJBR Description Reserved Transmit jabber frame counter.
PAGE 981
Enhanced Three-Speed Ethernet Controllers 16.5.3.6.40 Transmit Control Frame Counter (TXCF) Figure 16-90 describes the definition for the TXCF register. Offset eTSEC1:0x2_4720; eTSEC2:0x2_5720 Access: Read/Write 0 19 20 R — W Reset 31 TXCF All zeros Figure 16-90. Transmit Control Frame Counter Register Definition Table 16-94 describes the fields of the TXCF register. Table 16-94. TXCF Field Descriptions Bits Name 0–19 — 20–31 TXCF Description Reserved Transmit control frame counter.
PAGE 982
Enhanced Three-Speed Ethernet Controllers 16.5.3.6.42 Transmit Undersize Frame Counter (TUND) Figure 16-92 describes the definition for the TUND register. Offset eTSEC1:0x2_4728; eTSEC2:0x2_5728 Access: Read/Write 0 19 20 R — W Reset 31 TUND All zeros Figure 16-92. Transmit Undersize Frame Counter Register Definition Table 16-96 describes the fields of the TUND register. Table 16-96. TUND Field Descriptions Bits Name 0–19 — 20–31 TUND Description Reserved Transmit undersize frame counter.
PAGE 983
Enhanced Three-Speed Ethernet Controllers 16.5.3.6.44 Carry Register 1 (CAR1) Carry register bits are cleared on carry register writes when the respective bits are set. Figure 16-94 describes the definition for the CAR1 register.
PAGE 984
Enhanced Three-Speed Ethernet Controllers Table 16-98. CAR1 Field Descriptions (continued) Bits Name Description 25 C1RCD Carry register 1 RCDE counter carry bit 26 C1RCS Carry register 1 RCSE counter carry bit 27 C1RUN Carry register 1 RUND counter carry bit 28 C1ROV Carry register 1 ROVR counter carry bit 29 C1RFR Carry register 1 RFRG counter carry bit 30 C1RJB Carry register 1 RJBR counter carry bit 31 C1RDR Carry register 1 RDRP counter carry bit 16.5.3.6.
PAGE 985
Enhanced Three-Speed Ethernet Controllers Table 16-99.
PAGE 986
Enhanced Three-Speed Ethernet Controllers Table 16-100.
PAGE 987
Enhanced Three-Speed Ethernet Controllers 16.5.3.6.47 Carry Mask Register 2 (CAM2) While one of the below mask bits are cleared, the corresponding carry bit in CAR2 is allowed to cause interrupt indications in register IEVENT[MSR0]. These bits default to a set state. Figure 16-97 describes the definition for the CAM2 register.
PAGE 988
Enhanced Three-Speed Ethernet Controllers Table 16-101. CAM2 Field Descriptions (continued) Bits Name 30 — 31 M2TDP Description Reserved Mask register 2 TDRP counter carry bit mask 16.5.3.6.48 Receive Filer Rejected Packet Counter (RREJ) Figure 16-98 describes the definition for the RREJ register. Offset eTSEC1:0x2_4740; eTSEC2:0x2_5740 0 9 R Access: Read/Write 10 31 — W RREJ Reset All zeros Figure 16-98.
PAGE 989
Enhanced Three-Speed Ethernet Controllers 16.5.3.7.1 Individual/Group Address Registers 0–7 (IGADDRn) The IGADDRn registers are written by the user. Together these registers represent, depending on RCTRL[GHTX], either the 256 entries of the individual address hash table, or the first 256 entries of the extended group address hash table used in the address recognition process. The user can enable a hash entry by setting the appropriate bit.
PAGE 990
Enhanced Three-Speed Ethernet Controllers Table 16-104 describes the fields of the GADDRn register. Table 16-104. GADDRn Field Descriptions Bits 0–31 Name Description GADDRn Represents the 32-bit value associated with the corresponding register. When RCTRL[GHTX] = 0, GADDR0 contains entries 0–31 of the 256-entry group hash table and GADDR7 represents entries 224–255. When RCTRL[GHTX] = 1, GADDR0 contains entries 256–287 of the 512-entry extended group hash table and GADDR7 represents entries 480–511.
PAGE 991
Enhanced Three-Speed Ethernet Controllers Offset eTSEC1:0x2_4BFC; eTSEC2:0x2_5BFC 0 R W 1 2 Access: Read/Write 12 13 — EL Reset 17 18 — 25 26 EI 31 — All zeros Figure 16-102. ATTRELI Register Definition Table 16-106 describes the fields of the ATTRELI register. Table 16-106. ATTRELI Field Descriptions Bits Name 0–1 — Reserved 2–12 EL Extracted length. Specifies the number of bytes, as a multiple of 8 bytes, to extract from the receive frame.
PAGE 992
Enhanced Three-Speed Ethernet Controllers Offset eTSEC1:0x2_4C00+4n; eTSEC2:0x2_5C00+4n 0 R 7 Access: Read/Write 8 31 FBTHR W LEN Reset All zeros Figure 16-103. RQPRM Register Definition Table 16-107 describes the fields of the RQPRM register. Table 16-107. RQPRM Field Descriptions Bits Name Description 0–7 FBTHR Free BD threshold. Minimum number of BDs required for normal operation.
PAGE 993
Enhanced Three-Speed Ethernet Controllers Table 16-108 describes the fields of the RFBPTRn registers. Table 16-108. RFBPTR0–RFBPTR7 Field Descriptions Bits Name Description 0–28 RFBPTR Pointer to the last free BD in RxBD Ring n. When RBASEn is updated, eTSEC initializes RFBPTRn to the value in the corresponding RBASEn. Software may update this register at any time to inform the eTSEC the location of the last free BD in the ring.
PAGE 994
Enhanced Three-Speed Ethernet Controllers Table 16-109 describes the fields of the TMR_CTRL register. Register fields not described below are reserved. Table 16-109.
PAGE 995
Enhanced Three-Speed Ethernet Controllers Table 16-109. TMR_CTRL Register Field Descriptions (continued) Bits Name Description 25 CIPH Oscillator input clock phase. 0 non-inverted timer input clock 1 inverted timer input clock (NOTE: this setting is reserved if CKSEL=01.) 26 TMSR Timer soft reset. When enabled, it resets all the timer registers and state machines.
PAGE 996
Enhanced Three-Speed Ethernet Controllers Offset eTSEC1:0x2_4E04 Access: w1c 0 5 R — W Reset 6 7 ETS2 ETS1 w1c w1c 8 13 14 15 ALM2 ALM1 — w1c w1c All zeros 16 23 R — W Reset 24 25 26 PP1 PP2 PP3 w1c w1c w1c 27 31 — All zeros Figure 16-106. TMR_TEVENT Register Definition Table 16-110 describes the fields of the TMR_TEVENT register fields for the timer. Table 16-110.
PAGE 997
Enhanced Three-Speed Ethernet Controllers 16.5.3.10.3 Timer Event Mask Register (TMR_TEMASK) Timer event mask register. The event mask register provides control over which possible interrupt events in the TMR_TEVENT register are permitted to participate in generating hardware interrupts to the PIC. All implemented bits in this register are R/W and cleared upon a hardware reset. Figure 16-111 describes the definition for the TMR_TEMASK register.
PAGE 998
Enhanced Three-Speed Ethernet Controllers Offset eTSEC1:0x2_4E0C Access: Read/Write 0 15 R — W Reset All zeros 16 21 R — W Reset 22 23 TXP2 TXP1 24 30 — 31 RXP All zeros Figure 16-107. TMR_PEVENT Register Definition Table 16-113 describes the fields of the TMR_PEVENT register fields for the timer. Table 16-113.
PAGE 999
Enhanced Three-Speed Ethernet Controllers Table 16-114 describes the fields of the TMR_PEMASK register fields for the timer. Table 16-114. TMR_PEMASK Register Field Descriptions Bits Name Description 0–21 — 22 TXP2EN Transmit PTP packet event 2 enable 23 TXP1EN Transmit PTP packet event 1 enable 24–30 — 31 RXPEN Reserved Reserved Receive PTP packet event enable 16.5.3.10.6 Timer Status Register (TMR_STAT) This register requires the eTSEC filer to be enabled (via RCTRL[FILREN]).
PAGE 1000
Enhanced Three-Speed Ethernet Controllers Offset eTSEC1:0x2_4E18 (H); 0x2_4E1C (L) 0 Access: Read/Write 31 32 R 63 TMR_CNT_L TMR_CNT_H W Reset All zeros Figure 16-109. TMR_CNT_H Register Definition Table 16-117 describes the fields of the TMR_CNT_H/L register. Table 16-117. TMR_CNT_H/L Register Field Descriptions Bits 0–63 Name Description TMR_CNT_ Value of the current time counter. Current time is calculated by adding TMROFF_H/L with the H/L TMR_CNT_H/L counter.
PAGE 1001
Enhanced Three-Speed Ethernet Controllers Table 16-118 describes the fields of the TMR_ADD register fields for the timer. Table 16-118. TMR_ADD Register Field Descriptions Bits Name Description 0–31 ADDEND Timer drift compensation addend register value. It is programmed with a value of 2^32/FreqDivRatio. For example, TimerOsc = 50 MHz NominalFreq = 40 MHz FreqDivRatio = 1.25 ADDEND = ceil(2^32/1.25) = 0xCCCC_CCCD 16.5.3.10.
PAGE 1002
Enhanced Three-Speed Ethernet Controllers Table 16-120 describes the fields of the TMR_PRSC register. Table 16-120. TMR_PRSC Register Field Descriptions Bits Name 0–15 — 16–31 Description Reserved PRSC_OCK Output clock division/prescale factor. Output clock is generated by dividing the timer input clock by this number. Programmed value in this field must be greater than 1. Any value less than 1 is treated as 2. 16.5.3.10.
PAGE 1003
Enhanced Three-Speed Ethernet Controllers Table 16-122 describes the fields of the TMR_ALARMn_H/L register. Table 16-122. TMR_ALARMn_H/L Register Field Descriptions Bits 0–63 Name Description ALARM_H/L Alarm time comparator register. The corresponding alarm event in TMR_TEVENT is set when the current time counter becomes equal to or greater than the alarm time compare value in TMR_ALARMn_L/H. Writing the TMR_ALARMn_L register deactivates the alarm event after it has fired.
PAGE 1004
Enhanced Three-Speed Ethernet Controllers The FIPER can get the following values: 80, 170, 260 ....... The three registers in eTSEC1 are shared for all eTSECs. Figure 16-115 describes the definition for the TMR_FIPER register. Offset eTSEC1:0x2_4E80+4*n Access: Read/Write 0 31 R FIPER W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 16-115. TMR_FIPERn Register Definition Table 16-123 describes the fields of the TMR_FIPER register.
PAGE 1005
Enhanced Three-Speed Ethernet Controllers • • Section 16.6.5, “Lossless Flow Control” Section 16.6.7, “Buffer Descriptors” 16.6.1 Connecting to Physical Interfaces on Ethernet This section describes how to connect the eTSEC to various interfaces: MII and RGMII. To avoid confusion, all of the buses follow the bus conventions used in the IEEE 802.3 specification because the PHYs follow the same conventions. (For instance, in the bus TSECn_TXD[3:0], bit 3 is the msb and bit 0 is the lsb).
PAGE 1006
Enhanced Three-Speed Ethernet Controllers IEEE 802.3z GMII. The RGMII reduces the number of signals required to interconnect the MAC and the PHY from a maximum of 28 signals (GMII) to 15 signals (GTX_CLK125 included) in a cost effective and technology independent manner. To accomplish this objective, the data paths and all associated control signals are multiplexed using both edges of the clock. For gigabit operation, the clocks operate at 125 MHz, and for 10/100 operation, the clocks operate at 2.
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Enhanced Three-Speed Ethernet Controllers 16.6.1.3 Ethernet Physical Interfaces Signal Summary Table 16-125 describes the signal multiplexing for MII interfaces. Table 16-125. RGMII and MII Signals Multiplexing RGMII Interface MII Interface Frequency 125 [MHz] Frequency 25 [MHz] Voltage 2.5 [V] Voltage 3.3 [V] Signals (TSECn_) I/O No. of Signals Signals (TSECn_) I/O No.
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Enhanced Three-Speed Ethernet Controllers 16.6.2 Gigabit Ethernet Controller Channel Operation This section describes the operation of the eTSEC. First, the software initialization sequence is described. Next, the software (Ethernet driver) interface for transmitting and receiving frames is reviewed. Frame filtering and receive filing algorithm features are also discussed. The section concludes with interrupt handling, inter-packet gap time, and loop back descriptions. 16.6.2.
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Enhanced Three-Speed Ethernet Controllers 2. For the transmission of Ethernet frames, TxBDs must first be built in memory, linked together as a ring, and pointed to by the TBASEn registers. A minimum of two buffer descriptors per ring is required, unless the ring is disabled. Setting the ring to a size of one causes the same frame to be transmitted twice. If TCP/IP off-load is to be enabled, the TxBD[TOE] bit must be set for each frame. 3.
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Enhanced Three-Speed Ethernet Controllers 14. Clear QHLT and RXF bits in RSTAT register by writing 1 to them. 15. Clear GRS/GTS bits in DMACTRL (do not change other bits) 16. Enable Tx_EN/Rx_EN in MACCFG1 register 16.6.2.3 Gigabit Ethernet Frame Transmission The Ethernet transmitter requires little core intervention. After the software driver initializes the system, the eTSEC begins to poll the first transmit buffer descriptor (TxBD) in TxBD ring 0 every 512 transmit clocks.
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Enhanced Three-Speed Ethernet Controllers • • MACCFG2[PAD/CRC] is set MACCFG2[CRC] is set The Tx_EN is negated after the FCS is sent. This notifies the PHY of the need to generate the illegal Manchester encoding that signifies the end of an Ethernet frame. Following the transmission of the FCS, the Ethernet controller writes the frame status bits into the BD and clears TxBD[R].
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Enhanced Three-Speed Ethernet Controllers After the buffer is filled, the eTSEC clears RxBD[E] and, if RxBD[I] is set, generates an interrupt. If the incoming frame is larger than the buffer, the Ethernet controller fetches the next RxBD in the table. If it is empty, the controller continues receiving the rest of the frame.
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Enhanced Three-Speed Ethernet Controllers • • The first TxBD of every frame containing a custom preamble has its PRE bit set An 8-byte custom preamble sequence appears before the Ethernet DA field in the first transmit data buffer The definition of the 8-byte custom preamble sequence is shown in Figure 16-119. Byte Offsets 0 1 2 3 4 5 6 7 8 9 10 11 12 0–1 PreOct0 PreOct1 2–3 PreOct2 PreOct3 4–5 PreOct4 PreOct5 6–7 PreOct6 13 14 15 Figure 16-119.
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Enhanced Three-Speed Ethernet Controllers The fields of the received preamble sequence are described in Table 16-129. Should the received preamble be shorter than the 7-octet sequence defined by IEEE Std. 802.3, initial bytes of the received preamble sequence hold undefined values. The standard start of frame delimiter (0xD5) is always omitted. Table 16-129. Received Preamble Field Descriptions Bytes Bits 0–1 0–7 PreOct0 Octet #0 of received preamble. This is the first octet of preamble received.
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Enhanced Three-Speed Ethernet Controllers 16.6.2.7.1 Destination Address Recognition and Frame Filtering The eTSEC can perform layer 2 frame filtering on the basis of destination Ethernet address (DA), as illustrated by the flowchart in Figure 16-121. Incoming Frame F F G F I/G Address? Exact Addr. Enable? T T Search of Exact Match MAC Address Table I Broadcast Address? Hash Search of Group/Extended Address Table Station Addr. Match? F Exact Addr.
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Enhanced Three-Speed Ethernet Controllers promiscuous mode it remains possible to program the filer to reject frames based on their higher-layer header contents. In the case of an individual address, the DA field of the received frame is compared with the physical address that the user programs in the station address registers (MACSTNADDR1 and MACSTNADDR2).
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Enhanced Three-Speed Ethernet Controllers #define BITS_PER_BYTE 8 /* crc32() Takes the array of bytes, macaddr[], representing an Ethernet MAC address and returns the CRC-32 result over these bytes, where each byte is used in bit-reversed form (Ethernet bit order). Index 0 of macaddr[] is the first byte of the address on the wire. Test case: the result of crc32 on {0x00, 0x01, 0x02, 0x03, 0x04, 0x05} should be 0xad0c28f3.
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Enhanced Three-Speed Ethernet Controllers 16.6.2.8 Flow Control Because collisions cannot occur in full-duplex mode, gigabit Ethernet can operate at the maximum rate. If the rate becomes too fast for a station’s receiver, the station’s transmitter can send flow-control frames to reduce the rate. Flow-control instructions are transferred by special frames of minimum frame size. The length/type fields of these frames have a special value. Table 16-130 lists the flow-control frame structure. Table 16-130.
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Enhanced Three-Speed Ethernet Controllers • • • • Process the TxBDs to reuse them if the IEVENT[TXB, TXF or TXE] were set. Consult register bits TSTAT[TXF0–TXF7] to determine which TxBD rings gave rise to the transmit interrupt in the case of TXF. If the transmit speed is fast or the interrupt delay is long, more than one transmit buffer may have been sent by the eTSEC; thus, it is important to check more than just one TxBD during the interrupt handler.
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Enhanced Three-Speed Ethernet Controllers 16.6.2.9.1 Interrupt Coalescing Interrupt coalescing offers the user the ability to contour the behavior of the eTSEC with regard to frame interrupts. Separate but identical mechanisms exist for both transmitted frames and received frames. In either case, frame interrupts require that software set the I-bit in RxBDs or TxBDs, and disable buffer interrupts (IEVENT[RXB] or IEVENT[TXB]).
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Enhanced Three-Speed Ethernet Controllers Table 16-133. Interrupt Coalescing Timing Threshold Ranges ICCS (Clock Source) eTSEC Interface Format and Frequency or eTSEC System Frequency Interrupt Coalescing Threshold Time Minimum (ICTT = 0x0001) Maximum (ICTT = 0xFFFF) 0 (I/F clock) 10Base-T at 2.5 MHz 25.6 s 1.68 s 0 (I/F clock) 100Base-T at 25 MHz 2.56 s 168 ms 0 (I/F clock) 1000Base-T at 125 MHz 0.51 s 33.6 ms 1 (sys. clock) eTSEC operating at 125 MHz 0.512 s 33.
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Enhanced Three-Speed Ethernet Controllers 16.6.2.12 Error-Handling Procedure The eTSEC reports frame reception and transmission error conditions using the channel BDs, the error counters, and the IEVENT register. Transmission errors are described in Table 16-134. Table 16-134. Transmission Errors Error Response Transmitter underrun Transmitter underrun can occur either after frame transmission has commenced, or in response to an incomplete sequence of TxBDs.
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Enhanced Three-Speed Ethernet Controllers Table 16-135. Reception Errors (continued) Error Description Parser error If the receive frame parser is enabled, a parse error can be flagged as a result of inconsistencies discovered between fields of the embedded packet headers. For example, the L2 header may indicate an IPv4 header, but the IP version number fails to match.
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Enhanced Three-Speed Ethernet Controllers of the CPU cycles that would otherwise be spent by the TCP/IP stack. IP packet fragmentation and re-assembly, and TCP stream establishment and tear-down are not performed in hardware. The frame parser sets RQFPR[IPF] status flag encountering a fragmented frame.
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Enhanced Three-Speed Ethernet Controllers 16.6.3.2 Transmit Path Off-Load and Tx PTP Packet Parsing TOE functions for transmit are defined by the contents of the Tx FCB. Figure 16-123 describes the definition for the Tx FCB. Offset + 0 0 1 2 VLN IP IP6 Offset + 2 3 4 5 6 7 8 9 10 11 12 TUP UDP CIP CTU NPH 13 14 15 PTP L4OS L3OS Offset + 4 PHCS Offset + 6 VLCTL Figure 16-123.
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Enhanced Three-Speed Ethernet Controllers Table 16-136. Tx Frame Control Block Description (continued) Bytes Bits Name 0–1 5 CIP Checksum IP header enable. 0 Do not generate an IP header checksum. 1 Generate an IPv4 header checksum. 6 CTU Checksum TCP or UDP header enable. 0 Do not generate a TCP or UDP header checksum. RFC 768 advises that UDP packets not requiring checksum validation should have their checksum field set to zero. 1 Generate a TCP header checksum if IP = 1 and TUP = 1 and UDP = 0.
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Enhanced Three-Speed Ethernet Controllers The contents of the Rx FCB are defined in Table 16-137. Table 16-137. Rx Frame Control Block Descriptions Bytes Bits Name 0–1 0 VLN 1 IP Description VLAN tag recognized. This bit is set only if RCTRL[VLEX] is set. 0 No VLAN tag recognized. 1 IEEE Std. 802.1Q VLAN tag found; VLAN control word in VLCTL is valid. IP header found at layer 3.RCTRL[PRSDEP] must be set to 10 or 11 in order to enable IP discovery. See also IP6 bit of FCB.
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Enhanced Three-Speed Ethernet Controllers Table 16-137. Rx Frame Control Block Descriptions (continued) Bytes Bits Name Description 2–3 0–1 — Reserved 2–7 RQ Receive queue index. This index was selected by the eTSEC Rx Filer (from a matching Filer rule’s RQCTRL[Q] field) when it accepted the associated frame. If filing is not enabled, RQ is zero. Note that the 3 least significant bits of RQ correspond with the RxBD ring index whenever RCTRL[FSQEN] = 0.
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Enhanced Three-Speed Ethernet Controllers — — — — — — — JUMBO and SNAP header IPV4 IPV6 VLAN MPLSU/MPLSM PPPOES ARP For stack L2 (that is, more than one ethertypes) header, the Ethernet parser traverses through the header until it finds the last valid ethertype or the ethertype is unsupported. Table 16-138 describes what the Ethernet header parser recognizes for stack L2 header. Table 16-138.
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Enhanced Three-Speed Ethernet Controllers • • • IPv4 support — IPv4 source and destination addresses — 8-bit IPv4 type of service — IP layer 4 protocol / next header support – IPV4 – IPV4 Fragment.
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Enhanced Three-Speed Ethernet Controllers setting flags in the RQCTRL field. The eTSEC memory map provides access to these fields by way of an address register (RQFAR) and two porthole registers (RQFCR and RQFPR). 32 Bits 32 Bits Entry 0 RQCTRL RQPROP Entry 1 RQCTRL RQPROP Entry 2 RQCTRL RQPROP entry 255 RQCTRL RQPROP Access Index RQFAR Control/interpretation (Access through RQFCR) Filer Table Search Sequence Property Constant (Access through RQF Figure 16-125.
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Enhanced Three-Speed Ethernet Controllers • • • • The CMP field in RQCTRL determines how property PID is compared against RQPROP. Equality, inequality, greater-or-equal, and less-than compares are available. The AND field in RQCTRL allows more than one comparison in a sequence to be chained together as a Boolean AND condition. Setting AND = 1 defers evaluation of the rule until the next entry has been matched, which may, in turn, have AND set.
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Enhanced Three-Speed Ethernet Controllers 16.6.4.2.3 Special-Case Rules It is frequently useful to create rules that are guaranteed to succeed or fail, specifically to enforce a default filing decision or act as null entries. Suggested constructions for such rules are shown in Table 16-139. Table 16-139.
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Enhanced Three-Speed Ethernet Controllers 16.6.4.2.5 Setting Up the Receive Queue Filer Table The eTSEC frame parser always provides values for all properties, even where the relevant headers are not available. In the latter case, the filer is given default properties that can be used to avoid conflict with normal, defined property values.
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Enhanced Three-Speed Ethernet Controllers Table 16-141. Filer Table Example—802.1p Priority Filing (continued) Table Entry RQCTRL Fields RQPROP CLE REJ AND Q CMP PID Comment RQCTRL Word 6 0 0 0 000_110 00 1001 0x0000_0001 File priority 1 to ring 6 0x0000_1809 7 0 0 0 000_111 00 1001 0x0000_0000 File undefined 802.1p or priority 0 to ring 7—Default always matches 0x0000_1C09 16.6.4.2.
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Enhanced Three-Speed Ethernet Controllers Table 16-143.
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Enhanced Three-Speed Ethernet Controllers 16.6.4.3.1 Priority-Based Queuing (PBQ) PBQ is the simplest scheduler decision policy. The enabled TxBD rings are assigned a priority value based on their index. Rings with a lower index have precedence over rings with higher indices, with priority assessed on a frame-by-frame basis. For example, frames in TxBD ring 0 have higher priority than frames in TxBD ring 1, and frames in TxBD ring 1 have higher priority than frames in TxBD ring 2, and so on.
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Enhanced Three-Speed Ethernet Controllers if ring_empty(ring) then credit[ring] = 0; endif endloop endloop The algorithm checks registers TQUEUE[EN0–EN7] for enabled(), TSTAT[THLT0–THLT7] for ring_empty(), and TRxWT for weight(). For TxBD ring k, having a weight WTk, the long term average throughput for that ring is: rate of queue[k] (K = 1 to 7) = (available bandwidth) * WTk/(sum(WTi) + 6WT0) rate of queue(0) = (available bandwidth) * 7 * WT0/(sum(WTi) + 6WT0) where i = 0 to 7 16.6.
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Enhanced Three-Speed Ethernet Controllers • • • The eTSEC has just started transmitting a large frame and thus cannot send out a pause frame Upon reception of the pause request the far-end has just started transmission of a large frame The eTSEC receives a burst of short frames with minimum inter-frame-gap (96-bit times for Ethernet) Once the user has determined the worst case scenario for their application, they program the required free BD threshold into the eTSEC (through RQPRM[PBTHR]).
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Enhanced Three-Speed Ethernet Controllers a subsequent time, the wrap condition is successfully detected and hardware recognizes a nearly full ring (rather than a nearly empty one). Since software can increment RFBPTRn by any amount, it is not possible for hardware to determine in this case whether the user has cleared the entire ring or just one BD.
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Enhanced Three-Speed Ethernet Controllers 16.6.6 Hardware Assist for IEEE Std. 1588 Compliant Timestamping There is a push in industrial control applications to use Ethernet as the principal link layer for communications. This requires Ethernet to be used for both data transfer and real-time control. For real-time systems, each node is required to be synchronized to a master clock.
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Enhanced Three-Speed Ethernet Controllers 16.6.6.2 Timer Logic Overview The 1588 timer module can be partitioned into four different sub-modules as shown in Figure 16-126. 1588 Timer Clock Time Stamp Register Array TMRCK eTSEC TMRREG SEL SFD Detection Rx & Tx Ethernet MAC TMRMAC Rx Pins Tx Pins Figure 16-126. 1588 Timer Design Partition 16.6.6.
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Enhanced Three-Speed Ethernet Controllers relative to the SFD detection. Thus, the offset from the [1558] specified sample point can be accounted for in the PTP software implementation. 16.6.6.4 PTP Packet Parsing PTP packets are typically embedded within a UDP payload with special IP source and destination address and special source and destination ports numbers. Special fields of interest of a PTP packet are listed in Table 16-144. Table 16-144.
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Enhanced Three-Speed Ethernet Controllers A representation of the PTP packet is shown in Figure 16-128. Preamble SFD SRC DEST 10101011 L/T Data IP_H UDP_H CRC PTP_Message Time Stamp Point Figure 16-128. PTP Packet Format 16.6.6.4.1 General Purpose Filer Rule The eTSEC receive filer has been enhanced with the addition of a general-purpose event bit.
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Enhanced Three-Speed Ethernet Controllers Table 16-145. Time-Stamp Insertion Programming Requirements Requirement Behavior if requirement is not met TMR_CTRL[RTPE]=1 If TMR_CTRL[RTPE]=0, then no time-stamp is written to a TxPAL. TxBD[TOE]=1 If TxBD[TOE]=0, then no time-stamp is written to a TxPAL.
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Enhanced Three-Speed Ethernet Controllers Figure 16-129 depicts the buffer format requirements for time-stamp insertion on transmit packets. External Memory 32B cache-lines TX BD Ring 0 1 TOE=1 Data Buffer Length=8 Data Buffer Pointer 2 3 ... 7 FCB TxFCB TxPAL Data Buffer Length=M Data Buffer Pointer TxPAL TxPAL Unknown Unknown FRAME 8 Bytes Figure 16-129. Buffer Format for Transmit Time-Stamp Insertion 16.6.6.5.
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Enhanced Three-Speed Ethernet Controllers The contents of the Tx FCB are defined in Table 16-146. Table 16-146. Tx Frame Control Block Description Bytes Bits Name Description 0–1 0 VLN VLAN control word valid. This bit is ignored when the PTP bit is set. VLAN tag is read from the DFVLAN register if PTP=1. 0 Ignore VLCTL field. 1 If VLAN tag insertion is enabled for eTSEC, use the VLCTL field as the VLAN control word. 1 IP Layer 3 header is an IP header. 0 Ignore layer 3 and higher headers.
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Enhanced Three-Speed Ethernet Controllers Table 16-146. Tx Frame Control Block Description (continued) Bytes Bits Name Description 4–5 0–15 PHCS Pseudo-header checksum (16-bit one’s complement sum with carry wraparound, but without result inversion) for TCP or UDP packets, calculated by software. Valid only if NPH = 1. 6–7 0–15 VLCTL/ PTP_ID VLAN control word for insertion in the transmitted VLAN tag. Valid only if VLN = 1.Tx PTP packet identification number.
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Enhanced Three-Speed Ethernet Controllers Memory Map System Memory Tx Buffer Descriptors Status & Control TxBD Table Pointer (TBASEn) TxBD Table for Ring n RxBD Table Pointer (RBASEn) Tx Buffer Data Length Buffer Pointer Rx Buffer Descriptors RxBD Table for Ring n Status & Control Data Length Buffer Pointer Rx Buffer Figure 16-131. Example of eTSEC Memory Structure for BDs Beginning BD pointer 0 1 4 W =1 2 3 Figure 16-132. Buffer Descriptor Ring 16.6.7.
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Enhanced Three-Speed Ethernet Controllers The eTSEC clears the R bit in the first word of the BD after it finishes using the data buffer. The transfer status bits are then updated. Additional transmit frame status can be found in statistic counters in the MIB block. Software must expect eTSEC to prefetch multiple TxBDs, and for TCP/IP checksumming an entire frame must be read from memory before a checksum can be computed.
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Enhanced Three-Speed Ethernet Controllers The TxBD fields are detailed in Table 16-147. Table 16-147. Transmit Data Buffer Descriptor (TxBD) Field Descriptions Offset Bits Name Description 0–1 0 R Ready, written by eTSEC and user. 0 The data buffer associated with this BD is not ready for transmission. The user is free to manipulate this BD or its associated data buffer. The eTSEC clears this bit after the buffer is transmitted or after an error condition is encountered.
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Enhanced Three-Speed Ethernet Controllers Table 16-147. Transmit Data Buffer Descriptor (TxBD) Field Descriptions (continued) Offset Bits Name Description 0–1 5 TC Tx CRC. Written by user. (Valid only while it is set in first BD and TxBD[PAD/CRC] is cleared and MACCFG2[PAD/CRC enable] is cleared and MACCFG2[CRC enable] is cleared.) If MACCFG2[PAD/CRC enable] is set or MACCFG2[CRC enable] is set, this bit is ignored in ethernet modes.
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Enhanced Three-Speed Ethernet Controllers Table 16-147. Transmit Data Buffer Descriptor (TxBD) Field Descriptions (continued) Offset Bits Name Description 0–1 14 UN Underrun. Written by the eTSEC. 0 No underrun encountered (data was retrieved from external memory in time to send a complete frame). 1 The Ethernet controller encountered a transmitter underrun condition while sending the associated buffer. This could also have occurred in relation to a bus error causing IEVENT[EBERR].
PAGE 1054
Enhanced Three-Speed Ethernet Controllers The RxBD definition is interpreted by eTSEC hardware as if RxBDs mapped to C data structures in the manner illustrated by Figure 16-135. typedef unsigned short uint_16; /* choose 16-bit native type */ typedef unsigned int uint_32; /* choose 32-bit native type */ typedef struct rxbd_struct { uint_16 flags; uint_16 length; uint_32 bufptr; } rxbd; Figure 16-135. Mapping of RxBDs to a C Data Structure Table 16-148 describes the fields of the RxBD. Table 16-148.
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Enhanced Three-Speed Ethernet Controllers Table 16-148. Receive Buffer Descriptor Field Descriptions (continued) Offset Bits 0–1 Name Description 8 BC Broadcast. Written by the eTSEC. (Only valid if L is set.) Is set if the DA is broadcast (FF-FF-FF-FF-FF-FF). 9 MC Multicast. Written by the eTSEC. (Only valid if L is set.) Is set if the DA is multicast and not BC. 10 LG Rx frame length violation, written by the eTSEC (only valid if L is set).
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Enhanced Three-Speed Ethernet Controllers 16.7.1 Interface Mode Configuration This section describes how to configure the eTSEC in different supported interface modes. These include the following: • MII • RGMII The pinout, the data registers that must be initialized, as well as speed selection options are described. 16.7.1.1 MII Interface Mode Table 16-149 describes the signal configurations required for MII interface mode. Table 16-149.
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Enhanced Three-Speed Ethernet Controllers Table 16-150 describes the shared signals of the MII interface. Table 16-150. Shared MII Signals eTSEC Signals I/O No. of Signals MII Signals I/O No. of Signals Function MDIO I/O 1 MDIO I/O 1 Management interface I/O MDC O 1 MDC O 1 Management interface clock 2 Sum Sum 2 Table 16-151 describes the register initializations required to configure the eTSEC in MII mode. Table 16-151.
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Enhanced Three-Speed Ethernet Controllers Table 16-151. MII Mode Register Initialization Steps (continued) Set up the MII Mgmt for a write cycle to the external PHY Extended PHY control register #1 to set up the interface mode selection. MIIMADD[0000_0000_0000_0000_0000_0000_0001_0111] Perform an MII Mgmt write cycle to the external PHY.
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Enhanced Three-Speed Ethernet Controllers Table 16-151. MII Mode Register Initialization Steps (continued) Initialize (Empty) Receive Descriptor ring and fill with empty buffers Initialize RBASE0–RBASE7, RBASE0–RBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000] Enable Transmit Queues Initialize TQUEUE Enable Receive Queues Initialize RQUEUE Enable Rx and Tx, MACCFG1[0000_0000_0000_0000_0000_0000_0000_0101] 16.7.1.
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Enhanced Three-Speed Ethernet Controllers Table 16-153 describes the shared signals for the RGMII interface. Table 16-153. Shared RGMII Signals eTSEC Signals I/O No. of Signals GMII Signals I/O No. of Signals Function MDIO I/O 1 MDIO I/O 1 Management interface I/O MDC O 1 MDC O 1 Management interface clock Sum 2 Sum 2 Table 16-154 describes the register initializations required to configure the eTSEC in RGMII mode. Table 16-154.
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Enhanced Three-Speed Ethernet Controllers Table 16-154. RGMII Mode Register Initialization Steps (continued) Set up the MII Mgmt for a write cycle to the external PHY Control register (write the PHY address and Register address), MIIMADD[0000_0000_0000_0000_0001_0001_0000_0000] The control register (CR) is at offset address 0x00 from the external PHY address. (in this case 0x11) Perform an MII Mgmt write cycle to the external PHY.
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Enhanced Three-Speed Ethernet Controllers Table 16-154.
PAGE 1063
Chapter 17 I2C Interface This chapter describes the inter-IC (IIC or I2C) bus interface implemented on this device. 17.1 Introduction The inter-IC (IIC or I2C) bus is a two-wire—serial data (SDA) and serial clock (SCL)—bidirectional serial bus that provides a simple, efficient method of data exchange between this device and other devices, such as microcontrollers, EEPROMs, real-time clock devices, A/D converters, and LCDs. Figure 17-1 shows a block diagram of an instance of I2C interface.
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I2C Interface MPC8308 has two instances of I2C controllers. I2C controller 1 is used for boot sequencing and I2C controller 2 is used for data communication. 17.1.
PAGE 1065
I2C Interface HRESET is negated, the device may be initialized using boot sequence mode according to the BOOTSEQ field in the reset configuration word. See Section 17.4.5, “Boot Sequencer Mode.” Additionally, the following three I2C–specific states are defined for the I2C interface: • START condition—This condition denotes the beginning of a new data transfer (each data transfer contains several bytes of data) and awakens all slaves.
PAGE 1066
I2C Interface function is performed on both of these signals with external pull-up resistors. For electrical characteristics, see MPC8308 PowerQUICC II Pro Processor Hardware Specification. Table 17-2. I2C Interface Signals—Detailed Signal Descriptions Signal I/O Description I/O Serial clock. Performs as an input when the device is programmed as an I2C slave. SCL also performs as an output when the device is programmed as an I2C master.
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I2C Interface 17.3.1 Register Descriptions This section describes the I2C registers in detail. Note that reserved bits should always be written with the value they return when read. That is, the register should be programmed by reading the value, modifying appropriate fields, and writing back the value. The return value of the reserved fields should not be assumed, even though the reserved fields return zero. This does not apply to the I2C data register (I2CDR). I2C Address Register (I2CADR) 17.3.1.
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I2C Interface controller clock and CSB is 1:1.Clock ratios for I2C1 as well as I2C2 are not programmable; they are always 1:1 with CSB. Consider this factor when selecting an FDR value. Table 17-5. I2C FDR Field Descriptions Bits Name 0–1 — 2–7 FDR Description Reserved, should be cleared Frequency divider ratio. Used to prescale the clock for bit-rate selection. The serial bit clock frequency of SCL is equal to the I2C controller clock divided by the divider.
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I2C Interface Table 17-6 describes the I2CCR bit settings. . Table 17-6. I2CCR Field Descriptions Bits Name Description 0 MEN Module enable. Controls the software reset of the I2C module. 0 The module is reset and disabled. The interface is held in reset, but the registers can still be accessed. 1 The I2C module is enabled. MEN must be set before any other control register bits have any effect. All I2C registers for slave receive or master START can be initialized before setting this bit.
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I2C Interface 17.3.1.4 I2C Status Register (I2CSR) I2CSR is shown in Figure 17-5. Offset 0x0_300C Access: R/W 0x0_310C R 0 1 2 MCF MAAS MBB 1 0 0 W Reset 3 MAL 0 4 5 BCSTM SRW 0 0 6 MIF 0 7 RXAK 1 Figure 17-5. I2C Status Register (I2CSR) Table 17-7 describes the bit settings of the I2CSR. Table 17-7. I2CSR Field Descriptions Bits Name Description 0 MCF Data transfer. When one byte of data is transferred, the bit is cleared.
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I2C Interface Table 17-7. I2CSR Field Descriptions (continued) Bits Name Description 6 MIF Module interrupt. The MIF bit is set when an interrupt is pending, causing a processor interrupt request (provided I2CCR[MIEN] is set). 0 No interrupt is pending. Can be cleared only by software. 1 Interrupt is pending. MIF is set when one of the following events occurs: • One byte of data is transferred (set at the falling edge of the 9th clock).
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I2C Interface 17.3.1.6 Digital Filter Sampling Rate Register (I2CDFSRR) I2CDFSRR is shown in Figure 17-7. Offset 0x0_3014 Access: Read/write 0x0_3114 0 R 1 2 7 — W Reset 0 DFSR 0 0 1 0 0 0 0 Figure 17-7. I2C Digital Filter Sampling Rate Register (I2CDFSRR) Table 17-9 shows the I2CDFSRR field descriptions. Table 17-9. I2CDFSRR Field Descriptions Bits 0–1 2–7 17.4 Name — Description Reserved, should be cleared DFSR Digital filter sampling rate.
PAGE 1073
I2C Interface Figure 17-8 shows the interaction of these four parts with the calling address, data byte, and new calling address components of the I2C protocol. The details of the protocol are described in the following subsections.
PAGE 1074
I2C Interface broadcast message is the master address. Because the second byte is automatically acknowledged by hardware, the receiver device software must verify that the broadcast message is intended for itself by reading the second byte of the message. If the master address is for another receiver device and the third byte is a write command, the software can ignore the third byte during the broadcast.
PAGE 1075
I2C Interface • • Data transfers in progress are canceled when a STOP condition is detected or if there is a slave address mismatch. Cancellation of data transactions resets the clock module. The bus is detected to be busy upon the detection of a START condition and idle upon the detection of a STOP condition. 17.4.1.5.2 Control Transfer—Implementation Details The I2C module contains logic that controls the output to the serial data (SDA) and serial clock (SCL) lines of the I2C.
PAGE 1076
I2C Interface 17.4.1.6 Address Compare—Implementation Details The address compare block determines whether a slave has been properly addressed, either by its slave address or by the general broadcast address (which addresses all slaves).
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I2C Interface 17.4.3 Handshaking The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices can hold SCL low after completion of a 1-byte transfer (9 bits). In such cases, it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line. 17.4.4 Clock Control The clock control block handles requests from the clock signal for transferring and controlling data for multiple tasks.
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I2C Interface 17.4.4.2.2 Filtering of SCL and SDA Lines The SCL and SDA inputs are filtered to eliminate noise. Three consecutive samples of the SCL and SDA lines are compared to a pre-determined sampling rate. If they are all high, the output of the filter is high. If they are all low, the output is low. If they are any combination of highs and lows, the output is whatever the value of the line was in the previous clock cycle.
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I2C Interface Note that this usage does not prevent using the I2C boot sequencer to initiate the device in the normal functional mode, after reset state has completed. However, an I2C serial EEPROM of extended addressing type must be used and the first two EEPROM data structures must contain dedicated reset information. 17.4.5.2 EEPROM Calling Address The EEPROM calling address is 0b101_0000. The first EEPROM to be addressed must be programmed to respond to this address, or an error is generated.
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I2C Interface 17.4.5.3 EEPROM Data Format The I2C module expects a particular format for data to be programmed in the EEPROM. Figure 17-9 shows an example of the EEPROM contents, including the preamble, data format, and CRC.
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I2C Interface ACS BYTE_EN 1 ADDR[12–13] ADDR[14–21] ADDR[22–29] Second Configuration Preload Command DATA[0–7] DATA[8–15] DATA[16–23] DATA[24–31] ................ ACS BYTE_EN 1 ADDR[12–13] ADDR[14–21] ADDR[22–29] Last Configuration Preload Command DATA[0–7] DATA[8–15] DATA[16–23] DATA[24–31] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 End Command CRC[0–7] CRC[8–15] CRC[16–23] CRC[24–31] Figure 17-9.
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I2C Interface 0 ACS 1 2 3 4 BYTE_EN 5 CONT 6 7 ADDR[12:13] ADDR[14:21] ADDR[12:29] DATA[0:7] DATA[8:15] DATA[16:23] DATA[24:31] Figure 17-10. EEPROM Data Format for One Register Preload Command — The first byte holds alternate configuration space (ACS), byte enables, and continue (CONT) attributes. — The 2 least-significant bits of the address are derived from BYTE_ENABLES[ADDRESS_OFFSET]. Therefore, the address offset programmed into the EEPROM preload should be a word offset.
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I2C Interface register and data that causes the setting of the required GPIO signal. The GPIO signal may be used for an external device or for debug purposes. 17.5 Initialization/Application Information This section describes some programming guidelines recommended for the I2C interface. Figure 17-11 is a recommended flowchart for I2C interrupt service routines. A sync assembly instruction must be executed after each I2C register read/write access to guarantee that register accesses occur in order.
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I2C Interface It is recommended that a sync instruction follow each I2C register read or write to guarantee that register accesses occur in order.
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I2C Interface 17.5.2 Initialization Sequence A hard reset initializes all of the I2C registers to their default states. The following initialization sequence initializes the I2C unit: 1. All I2C registers must be located in a cache-inhibited page. 2. Update I2CFDR[FDR] and select the required division ratio to obtain the SCL frequency from the CSB (platform) clock. 3. Update I2CADR to define the slave address for this device. 4.
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I2C Interface During slave-mode address cycles (I2CSR[MAAS] is set), I2CSR[SRW] should be read to determine the direction of the subsequent transfer and I2CCR[MTX] should be programmed accordingly. For slave-mode data cycles (MAAS is cleared), I2CSR[SRW] is not valid and I2CCR[MTX] must be read to determine the direction of the current transfer (see Figure 17-11). 17.5.5 Generation of STOP A data transfer ends with a STOP condition generated by the master device.
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I2C Interface 17.5.8.1 Slave Transmitter and Received Acknowledge In the slave transmitter routine, the received acknowledge bit (I2CSR[RXAK]) must be tested before sending the next byte of data. The master signals an end-of-data by not acknowledging the data transfer from the slave. When no acknowledge is received (I2CSR[RXAK] is set), the slave transmitter interrupt routine must clear I2CCR[MTX] to switch the slave from transmitter to receiver mode.
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I2C Interface MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev.
PAGE 1089
Chapter 18 DUART This chapter describes the two (dual) universal asynchronous receiver/transmitters (UARTs) of the device. It describes the functional operation, the DUART initialization sequence, and the programming details for the DUART registers and features. 18.1 Overview The DUART consists of two (dual) universal asynchronous receiver/transmitters (UARTs). The UARTs act independently; all references to UART refer to one of these receiver/transmitters. Each UART is clocked by the system clock.
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DUART 18.1.
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DUART 18.2 External Signal Descriptions This section contains a signal overview and detailed signal descriptions. 18.2.1 Signal Overview Table 18-1 summarizes the DUART signals. Note that although the actual device signal names are prepended with the ‘UART_’ prefix as shown in the table, the functional (abbreviated) signal names are often used throughout this chapter. Table 18-1.
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DUART All DUART registers are one byte wide; reads and writes to these registers must be byte-wide operations. Table 18-3 provides a register summary with references to the section and page that contain detailed information about each register. Undefined byte address spaces within offset 0x4000–0x4FFF are reserved. Table 18-3. DUART Register Summary Offset Register Access Reset Section/Page URBR—ULCR[DLAB] = 0 UART1 receiver buffer register R 0x0000 18.3.1.
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DUART Table 18-3. DUART Register Summary (continued) Offset Register 0x0_4607 USCR—ULCR[DLAB] = x UART2 scratch register 0x0_4610 UDSR—ULCR[DLAB] = x UART2 DMA status register 18.3.1 Access Reset Section/Page R/W 0x0000 18.3.1.10/18-14 R 0x0001 18.3.1.12/18-15 Register Descriptions The following sections describe the UART1 and UART2 registers. 18.3.1.1 Receiver Buffer Registers (URBR1 and URBR2) These registers contain the data received from the transmitter on the UART buses.
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DUART Figure 18-3 shows the bits in the UTHRs. Offset: 0x0_4500, 0x0_4600 Access: User write-only 0 7 R W DATA Reset All zeros Figure 18-3. Transmitter Holding Registers (UTHR1 and UTHR2) Table 18-5 describes the UTHR. Table 18-5. UTHR Field Descriptions Bits Name 0–7 DATA 18.3.1.
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DUART Figure 18-5 shows the bits in the UDLBs. Offset: 0x0_4500, 0x0_4600 Access: User read/write 0 7 R UDLB W Reset All zeros Figure 18-5. Divisor Least Significant Byte Registers (UDLB1 and UDLB2) Table 18-7 describes the UDLB. Table 18-7. UDLB Field Descriptions Bits Name Description 0–7 UDLB Divisor least significant byte. This is concatenated with UDMB. Table 18-8 shows baud rate for a variety of input clock frequencies. Table 18-8.
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DUART Figure 18-6 shows the bits in the UIER. Offset: 0x0_4501, 0x0_4601 Access: User read/write 0 3 R — W Reset 4 5 6 7 EMSI ERLSI ETHREI ERDAI All zeros Figure 18-6. Interrupt Enable Registers (UIER1 and UIER2) Table 18-9 describes the UIER fields. Table 18-9. UIER Field Descriptions Bits Name 0–3 — 4 EMSI Enable MODEM status interrupt 0 Mask interrupts caused by UMSR[DCTS] being set. 1 Enable and assert interrupts when UMSR[CTS] changes state.
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DUART Figure 18-7 shows the bits in the UIIR. Offset: 0x0_4502, 0x0_4602 0 R Access: User read-only 1 2 FE 3 — 4 5 6 7 IID3 IID2 IID1 IID0 0 0 0 1 W Reset 0 0 0 0 Figure 18-7. Interrupt ID Registers (UIIR1 and UIIR2) Table 18-10 describes the fields of the UIIR. Table 18-10. UIIR Field Descriptions Bits Name Description 0–1 FE FIFOs enabled. Reflects the setting of UFCR[FEN].
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DUART UFCR bits cannot be programmed unless FIFO enable bits are set. When changing from FIFO mode to 16450 mode (non-FIFO mode) and vice versa, data is automatically cleared from the FIFOs. After all of the bytes in the receiver FIFO are cleared, the receiver internal shift register is not cleared. Similarly, the bytes are cleared in the transmitter FIFO, but the transmitter internal shift register is not cleared. Both TFR and RFR are self clearing. Figure 18-8 shows the bits in the UFCRs.
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DUART After initializing ULCR, the software should not rewrite the ULCR while valid transfers on the UART bus are active. The software should not rewrite the ULCR until the last STOP bit is received and no new characters are being transferred on the bus. The stick parity bit, ULCR[SP], assigns a set parity value for the parity bit time slot sent on the UART bus. The set value is defined as mark parity (logic 1) or space parity (logic 0). ULCR[PEN] and ULCR[EPS] help determine the set parity value.
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DUART Table 18-14. Parity Selection Using ULCR[PEN], ULCR[SP], and ULCR[EPS] 18.3.1.8 PEN SP EPS Parity Selected 0 0 0 No parity 0 0 1 No parity 0 1 0 No parity 0 1 1 No parity 1 0 0 Odd parity 1 0 1 Even parity 1 1 0 Mark parity 1 1 1 Space parity MODEM Control Registers (UMCR1 and UMCR2) The UMCRs, shown in Figure 18-10, control the interface with the external peripheral device on the UART bus.
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DUART 18.3.1.9 Line Status Registers (ULSR1 and ULSR2) The ULSRs, shown in Figure 18-11, monitor the status of the data transfer on the UART buses. To isolate the status bits from the proper character received through the UART bus, software should read the ULSR and then the URBR. Offset: 0x0_4505, 0x0_4605 R Access: User read-only 0 1 2 3 4 5 6 7 RFE TEMT THRE BI FE PE OE DR 0 1 1 0 0 0 0 0 W Reset Figure 18-11.
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DUART Table 18-16. ULSR Field Descriptions (continued) Bits Name Description 6 OE Overrun error 0 Cleared when ULSR is read 1 Before URBR was read, it was overwritten with a new character. The old character is lost. In FIFO mode, the receiver FIFO is full (regardless of the receiver FIFO trigger level setting) and a new character has been received into the internal receiver shift register. The old character was overwritten by the new character. Data in the receiver FIFO was not overwritten.
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DUART Table 18-18 describes UAFR fields. Table 18-18. UAFR Field Descriptions Bits Name Description 0–5 — Reserved 6 BO Baud clock select 0 The baud clock is not gated off. 1 The baud clock is gated off. 7 CW Concurrent write enable 0 Disables writing to both UART1 and UART2. 1 Enables concurrent writes to corresponding UART registers. A write to a register in UART1 is also a write to the corresponding register in UART2 and vice versa. 18.3.1.
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DUART Table 18-20 and Table 18-21 show the set and cleared conditions for UDSR[TXRDY]. Table 18-20. UDSR[TXRDY] Set Conditions DMS FEN DMA Mode 0 0 0 0 1 0 1 0 0 1 1 1 Meaning TXRDY is set after the first character is loaded into the transmitter FIFO or UTHR. TXRDY is set when the transmitter FIFO is full. Table 18-21. UDSR[TXRDY] Cleared Conditions DMS FEN DMA Mode 0 0 0 0 1 0 1 0 0 1 1 1 Meaning TXRDY is cleared when there are no characters in the transmitter FIFO or UTHR.
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DUART The transmitter accepts parallel data with a write access to UTHR. In FIFO mode, the data is placed directly into an internal transmitter shift register, or into the transmitter FIFO—see Section 18.4.5, “FIFO Mode.” The transmitting registers convert the data to a serial bit stream by inserting the appropriate START, STOP, and optional parity bits. Finally, the registers output a composite serial data stream on the channel transmitter serial data output (SOUT).
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DUART 18.4.1.2 Data Transfer Each data transfer contains 5, 6, 7, or 8 bits of data. The ULCR data bit length for the transmitter and receiver UART devices must agree before a transfer begins; otherwise, a parity or framing error may occur. A transfer begins when UTHR is written. At that time, a START bit is generated followed by 5 to 8 of the data bits previously written to the UTHR. The data bits are driven from the least- to the most-significant bits.
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DUART 18.4.3 Local Loopback Mode Local loopback mode is provided for diagnostic testing. The data written to UTHR can be read from the receiver buffer register (URBR) of the same UART. The transmitter SOUT is set to a logic 1 and the receiver SIN is disconnected. The output of the transmitter shift register is looped back into the receiver shift register input. In this diagnostic mode, data that is transmitted is immediately received.
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DUART and set the FIFO receiver trigger level UFCR[RTL] to control the received data available interrupt UIER[ERDAI]. The UFCR also selects the type of DMA signaling. The UDSR[RXRDY] indicates the status of the receiver FIFO. UDSR[TXRDY] indicate when the transmitter FIFO is full. When in FIFO mode, data written to UTHR is placed into the transmitter FIFO. The first byte written to UTHR is the first byte onto the UART bus. 18.4.5.
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DUART 18.5 DUART Initialization/Application Information The following requirements must be met for DUART accesses: • All DUART registers must be mapped to a cache-inhibited and guarded area. (That is, the WIMG setting in the MMU needs to be 0b01x1.) • All DUART registers must be 1 byte wide. Reads and writes to these registers must be byte-length operations. A system reset puts the DUART registers to a default state.
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Chapter 19 Serial Peripheral Interface 19.1 Overview The serial peripheral interface (SPI) allows the device to exchange data between other PowerQUICC family chips, the MC68360, MC68302, M68HC11, and M68HC05 microcontroller families, and other family devices. The SPI can be used to communicate with peripheral devices such as EEPROMs, real-time clocks, A/D converters, and ISDN devices.
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Serial Peripheral Interface 19.1.
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Serial Peripheral Interface 19.1.3 Modes of Operation The SPI can be programmed to work in a single- or multiple-master environment. This section describes SPI master and slave operations in a single-master configuration. It also discusses the multiple master environment. The following sections summarize the main modes of operation that the SPI supports. 19.1.3.1 SPI as a Master Device In master mode, the SPI sends a message to the slave peripheral, which sends back a simultaneous reply.
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Serial Peripheral Interface The SPI sets SPIE[NF] to issue a maskable interrupt to the interrupt controller whenever its transmit buffer is not full. It also sets the NF bit after sending the last word. In response, the core should read the exception flags that relate to the last word. The SPI sets SPIE[NE] to issue a maskable interrupt to the interrupt controller whenever the receiver buffer has been filled with data. 19.1.3.
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Serial Peripheral Interface the output drivers of the SPI signals. The core must clear SPMODE[EN], correct the problems, and clear SPIE[MME] before the SPI can be used again. SPI #0 SPIMOSI SPIMISO SPICLK SPISEL SELOUT1 SELOUT2 SELOUT3 SPISEL0 SPISEL1 SPISEL2 SPISEL3 SPI #1 SPIMOSI SPIMISO SPICLK SPISEL SELOUT0 SELOUT2 SELOUT3 SPI #2 SPIMOSI SPIMISO SPICLK SPISEL SELOUT0 SELOUT1 SELOUT3 SPI #3 SPIMOSI SPIMISO SPICLK SPISEL SELOUT0 SELOUT1 SELOUT2 Notes: 1. All signals are open-drain. 2.
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Serial Peripheral Interface 19.2 External Signal Descriptions The SPI’s four wire interface consists of transmit, receive, clock, and slave select. 19.2.1 Overview Table 19-1 lists signal properties. Table 19-1.
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Serial Peripheral Interface Table 19-2. Detailed Signal Descriptions (continued) Signal I/O Description SPICLK I/O Serial clock in or serial clock out for slave or master mode respectively State Assertion/Negation according to SPMODE[PM,DIV16] register rate configuration Meaning Timing SPISEL I Assertion/Negation—during frame reception/transmission SPI slave select State Asserted—In slave mode declares the slave has been selected for the coming frame.
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Serial Peripheral Interface of IMMRBAR together with the SPI block base address and offset listed in Table 19-3. Undefined 4-byte address spaces within offset 0x000–0xFFF are reserved. Table 19-3. SPI Register Summary Offset Register Access Reset Value Section/Page Serial Peripheral Interface (SPI)—Block Base Address 0x0_7000 0x000–0x01F Reserved — — — R/W 0x0000_0000 19.3.1.1/1919-8 0x020 SPI mode register (SPMODE) 0x024 SPI event register (SPIE) Mixed 0x0000_0000 19.3.1.
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Serial Peripheral Interface Table 19-4. SPMODE Field Descriptions (continued) Bits Name 2 CI Clock invert. Inverts SPI clock polarity. See Figure 19-5 and Figure 19-6 for more information 0 The inactive state of SPICLK is low. 1 The inactive state of SPICLK is high. 3 CP Clock phase. Selects the transfer format. See Figure 19-5 and Figure 19-6 for more information. 0 SPICLK starts toggling at the middle of the data transfer. 1 SPICLK starts toggling at the beginning of the data transfer.
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Serial Peripheral Interface Table 19-4. SPMODE Field Descriptions (continued) Bits Name Description 19 OD Open drain mode. 0 All output pins are configured to normal mode. 1 All output pins are configured to open drain mode. 20–31 — Reserved. Should be cleared. Figure 19-5 shows the SPI transfer format in which SPICLK starts toggling in the middle of the transfer (SPMODE[CP] = 0).
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Serial Peripheral Interface ‘1’. Writing ‘0’ has no effect. Setting a bit in the SPI mask register (SPIM) enables, and clearing a bit masks the corresponding interrupt. Unmasked SPIE bits must be cleared before the core clears internal interrupt requests. Figure 19-7 shows SPI event register. Offset 0x024 Access: Mixed 0 16 R — 17 18 19 20 21 22 23 24 LT DNR OV UN MME NE NF 31 — w1c w1c w1c w1c w1c W Reset All zeros Figure 19-7.
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Serial Peripheral Interface SPIM bit enables and clearing a SPIM bit masks the corresponding interrupt. Unmasked SPIE bits must be cleared before the core clears its internal interrupt requests. Offset 0x028 Access: Read/write 0 16 17 R — W 18 19 20 21 22 23 LT DNR OV UN MME NE NF Reset 24 31 — All zeros Figure 19-8. SPIM—SPI Mask Register Definition Table 19-6 describes the SPIM fields. Table 19-6. SPIM Field Descriptions Bits Name Description 0–16 — Reserved, should be cleared.
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Serial Peripheral Interface 19.3.1.4 SPI Command Register (SPCOM) The SPI command register (SPCOM), shown in Figure 19-9, is used to end SPI operation. Offset 0x02C Access: Write only 0 8 R — W 9 10 31 — LST Reset All zeros Figure 19-9. SPI Command Register Definition Table 19-7 describes the SPCOM fields. Table 19-7. SPCOM Field Descriptions Bits Name 0–8 — 9 LST 10–31 — 19.3.1.5 Description Reserved, should be cleared. This bit represents the last character.
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Serial Peripheral Interface 19.3.1.6 SPI Receive Data Hold Register (SPIRD) SPIRD, shown in Figure 19-11, is used to receive a character of data from the SPI channel. Each time SPIE[NE] is set, the core can read SPIRD. Offset 0x034 Access: Read-only 0 31 R DATA W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 19-11. SPI Receive Data Hold Register Definition Table 19-9 shows the field descriptions of the SPI receive data hold register.
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Serial Peripheral Interface Access: Read-only 0 15 R — 16 17 MSB 30 DATA 31 LSB W Reset All ones Figure 19-15. Example SPMODE[REV] = 0 SPMODE[LEN] = 15 LSB Sent First 19.4 Initialization/Application Information The following sections describe programming examples of the SPI master and slave. 19.4.1 SPI Master Programming Example The following sequence initializes the SPI to run at a high speed in master mode: 1.
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Chapter 20 JTAG/Testing Support 20.1 Overview The device provides a JTAG (Joint Test Action Group) interface to facilitate boundary-scan testing. The JTAG interface complies to the IEEE 1149.1 boundary-scan specification. For additional information about JTAG operations, refer to the IEEE 1149.1 specification. The JTAG interface consists of a set of five signals, three JTAG registers (see Section 20.
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JTAG/Testing Support • Test clock (TCK) The TDI and TDO signals input and output all instructions and data to the JTAG scan registers. JTAG operations are controlled by the TAP controller through the TMS and TCK signals. Boundary-scan data is latched by the TAP controller on the rising edge of the TCK signal. The TRST signal is specified as optional by the IEEE 1149.1 specification, and is used to reset the TAP controller asynchronously.
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JTAG/Testing Support Table 20-2. JTAG Test—Detailed Signal Descriptions (continued) Signal I/O TDO O Description JTAG test data output. State Asserted/Negated—The contents of the selected internal instruction or data register are shifted out Meaning on this signal on the falling edge of TCK. Remains in a high-impedance state except when scanning data. Timing See IEEE 1149.1 specification for more details. TMS I JTAG test mode select.
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JTAG/Testing Support • The 8-bit JTAG instruction register serves as an instruction and status register. As TAP controller instructions are scanned in through the TDI input, the TAP controller status bits are scanned out through the TDO output. TAP controller The device provides a standard JTAG TAP controller that controls instruction and data scan operations. The TMS signal controls the state transitions of the TAP controller. MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev.
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Chapter 21 General Purpose I/O (GPIO) 21.1 Introduction This chapter describes the general-purpose I/O module, including pin descriptions, register settings, and interrupt capabilities. Figure 21-1 shows the block diagram of the GPIO module. GPDAT Register To/From Peripheral Bus GPIO[0:23] Register Interface GPIER/ GPIMR/ GPICR Registers gpio_int GPDIR/ GPODR Registers Figure 21-1. GPIO Module Block Diagram 21.1.1 Overview The GPIO module supports 24 general-purpose I/O ports.
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General Purpose I/O (GPIO) • • Open-drain capability on all ports All ports can optionally generate an interrupt upon changing their state. 21.2 External Signal Description The following section provides information about GPIO signals. 21.2.1 Signals Overview Table 21-1 provides detailed descriptions of the external GPIO signals. Table 21-1. GPIO—Signal Descriptions Signal I/O GPIO[0:23] Description I/O General purpose I/O.
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General Purpose I/O (GPIO) 21.3.1 GPIO Direction Register (GPDIR) The GPIO direction registers (GPDIR), shown in Figure 21-2, defines the direction of the individual ports. Offset 0xC00 Access: Read/write 0 23 24 R Dn W Reset 31 — All zeros Figure 21-2. GPIO Direction Register (GPDIR) Table 21-3 defines the bit fields of GPDIR. Table 21-3. GPDIR Bit Settings Bits Name 0–23 Dn Direction. Indicates whether a signal is used as an input or an output. 0 The corresponding signal is an input.
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General Purpose I/O (GPIO) 21.3.3 GPIO Data Register (GPDAT) The GPIO data register (GPDAT), shown in Figure 21-4, carries the data in/out for the individual ports. Offset 0xC08 Access: Read/write 0 23 24 R Dn W Reset 31 — All zeros Figure 21-4. GPIO Data Register (GPDAT) Table 21-5 defines the bit fields of GPDAT. Table 21-5. GPnDAT Bit Settings Bits Name Description 0–23 Dn Data. Write data is latched and presented on external signals if GPDIR has configured the port as an output.
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General Purpose I/O (GPIO) of the GPIMR state. When one or more non-masked interrupt events occur, the GPIO module issues an interrupt to the on chip interrupt controller. Offset 0xC10 Access: Read/write 0 23 24 R Dn W Reset 31 — All zeros Figure 21-6. GPIO Interrupt Mask Register (GPIMR) Table 21-7 defines the bit fields of GPIMR. Table 21-7. GPIMR Bit Settings Bits Name 0–23 Dn Interrupt mask. Indicates whether an interrupt event is masked or not masked.
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Appendix A Complete List of Configuration, Control, and Status Registers A.1 Local Access Windows Table A-1. Local Access Register Memory Map Local Access—Block Base Address 0x0_000 Local Memory Offset (Hex) Register 0x000 Internal memory map base address register (IMMRBAR) 0x004 Reserved 0x008 Alternate configuration base address register (ALTCBAR) 0x00C–0x01C Reserved Access Reset Section/Page R/W 0xFF40_0000 5.1.4.1/5-5 — — — R/W 0x0000_0000 5.1.4.2/5-7 — — — 5.1.4.
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Complete List of Configuration, Control, and Status Registers Table A-1. Local Access Register Memory Map (continued) Local Access—Block Base Address 0x0_000 Local Memory Offset (Hex) Register Access Reset Section/Page 0x0A8 DDR2 local access window 1 base address register (DDRLAWBAR1) R/W 0x0000_0000 5.1.4.7/5-11 0x0AC DDR2 local access window 1 attribute register (DDRLAWAR1) R/W 0x0000_0000 5.1.4.8/5-12 — — — 0x0B0–0x0FC Reserved 1 Depends on reset configuration word high values.
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Complete List of Configuration, Control, and Status Registers A.3 Watchdog Timer (WDT) Table A-3. Watchdog Timer (WDT) Registers Watchdog Timer (WDT)—Block Base Address 0x0_0200 Offset Register Access Reset Section/Page — — — 0x000–0x003 Reserved 0x004 System watchdog control register (SWCRR) R/W 0xFFFF_0003 or 0xFFFF_00071 5.3.4.1/5-34 0x008 System watchdog count register (SWCNR) R 0x0000_FFFF 5.3.4.2/5-35 — — — R/W 0x0000 5.3.4.
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Complete List of Configuration, Control, and Status Registers Table A-5. Periodic Interval Timer (PIT) Registers (continued) Periodic Interval Timer (PIT)—Block Base Address 0x0_0400 Offset Register 0x010 Periodic interval timer event register (PTEVR) 0x014–0x01F Reserved A.6 Access Reset Section/Page w1c 0x0000_0000 5.5.5.5/5-51 — — — General Purpose (Global) Timers (GTMs) Table A-6.
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Complete List of Configuration, Control, and Status Registers Table A-6. General Purpose (Global) Timers (GTMs) Registers (continued) Offset Register 0x038 Timer 1 global timers prescale register (GTPSR1) 0x03A Timer 2 global timers prescale register (GTPSR2) 0x03C Timer 3 global timers prescale register (GTPSR3) 0x03E Timer 4 global timers prescale register (GTPSR4) A.7 Access Reset Value Section/Page R/W 0x0003 5.6.5.7/5-65 Integrated Programmable Interrupt Controller (IPIC) Table A-7.
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Complete List of Configuration, Control, and Status Registers Table A-7. IPIC Registers (continued) Integrated Programmable Interrupt Controller—Block Base Address 0x0_0700 Offset Register Access Reset Value Section/Page 0x058 System external interrupt force register (SEFCR) R/W 0x0000_0000 8.5.20/8-29 0x05C System error force register (SERFR) R/W 0x0000_0000 8.5.21/8-29 0x060 System critical interrupt vector register (SCVCR) R 0x0000_0000 8.5.
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Complete List of Configuration, Control, and Status Registers Table A-9. Reset Configuration Registers (continued) Reset Configuration—Block Base Address 0x0_0900 Offset Register Access Reset Section/Page 0x010 Reset status register (RSR) R/W 0x0000_0000 4.5.1.3/4-26 0x014 Reset mode register (RMR) R/W 0x0000_0000 4.5.1.4/4-27 0x018 Reset protection register (RPR) R/W 0x0000_0000 4.5.1.5/4-28 0x01C Reset control register (RCR) R/W 0x0000_0000 4.5.1.
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Complete List of Configuration, Control, and Status Registers A.12 General Purpose I/O (GPIO) Table A-12. General Purpose I/O (GPIO) Registers General Purpose I/O (GPIO)—Block Base Address 0x0_0C00 Offset Register Access Reset Section/Page 0x000 GPIO direction register (GPDIR) R/W 0x0000_0000 21.3.1/21-3 0x004 GPIO open drain register (GPODR) R/W 0x0000_0000 21.3.2/21-3 0x008 GPIO data register (GPDAT) R/W 0x0000_0000 21.3.
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Complete List of Configuration, Control, and Status Registers Table A-13. DDR Memory Controller Registers (continued) DDR Memory Controller—Block Base Address 0x0_2000 1 Offset Register Access Reset Section/Page 0xE00 DATA_ERR_INJECT_HI—Memory data path error injection mask high R/W 0x0000_0000 9.4.1.18/9-30 0xE04 DATA_ERR_INJECT_LO—Memory data path error injection mask low R/W 0x0000_0000 9.4.1.19/9-31 0xE08 ERR_INJECT—Memory data path error injection mask ECC R/W 0x0000_0000 9.4.1.
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Complete List of Configuration, Control, and Status Registers A.15 DUART Table A-15. DUART Registers UART 1—Block Base Address 0x0_4000 UART 2—Block Base Address 0x0_4100 Offset Access Reset Section/Page URBR—ULCR[DLAB] = 0 UART1 receiver buffer register R 0x0000 18.3.1.1/18-5 UTHR—ULCR[DLAB] = 0 UART1 transmitter holding register W 0x0000 18.3.1.2/18-5 UDLB—ULCR[DLAB] = 1 UART1 divisor least significant byte register R/W 0x0000 18.3.1.
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Complete List of Configuration, Control, and Status Registers A.16 Enhanced Local Bus Controller (eLBC) Table A-16. Enhanced Local Bus Controller Registers Enhanced Local Bus Controller—Block Base Address 0x0_5000 Offset Register Access Reset Section/Page 0x000 BR0—Base register 0 R/W 0x0000_nnnn 10.3.1.1/10-9 0x008 BR1—Base register 1 R/W 0x0000_0000 10.3.1.1/10-9 0x010 BR2—Base register 2 R/W 0x0000_0000 10.3.1.1/10-9 0x018 BR3—Base register 3 R/W 0x0000_0000 10.3.1.
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Complete List of Configuration, Control, and Status Registers Table A-16. Enhanced Local Bus Controller Registers (continued) Enhanced Local Bus Controller—Block Base Address 0x0_5000 Offset Register Access Reset Section/Page w1c 0x0000_0000 10.3.1.14/10-29 — — — 0x0C4 LTECCR—Transfer error ECC register 0x0C8– 0x0CC Reserved 0x0D0 LBCR—Configuration register R/W 0x0004_0000 10.3.1.15/10-30 0x0D4 LCRR—Clock ratio register R/W 0x8000_0008 10.3.1.
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Complete List of Configuration, Control, and Status Registers A.18 DMA Controller Table A-18. DMA Controller Registers Block Base Address: 0x2_C000 Offset Register Access Reset Section/Page R/W 0x0000_E400 12.2.1/12-3 0x000 DMACR—DMA Control Register 0x004 DMAES—DMA Error Status Register R 0x0000_0000 12.3/12-6 0x008– 0x010 Reserved — — — 0x014 DMAEEI—DMA enable error interrupt register R/W 0x0000_0000 12.3.
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Complete List of Configuration, Control, and Status Registers A.19 PCI Express Controller Table A-20. PCI Express Controller Registers PCI Express—Block Base Address 0x0_9000 Offset Register Access Reset Section/Page PCI Express Controller Registers PCI Express Core Configuration Header Registers 0x000 PCI Express Vendor ID Register R 0x1957 14.4.1.1/14-15 0x002 PCI Express Device ID Register R Device-specific 14.4.1.2/14-15 0x004 PCI Express Command Register Mixed 0x0000 14.4.1.
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Complete List of Configuration, Control, and Status Registers Table A-20. PCI Express Controller Registers PCI Express—Block Base Address 0x0_9000 Offset Register only)1 Access Reset Section/Page R/W 0x0000 14.4.3.9/14-31 0x022 PCI Express Memory Limit Register (RC mode 0x024 PCI Express Prefetchable Memory Base Register (RC mode only)1 R/W 0x0000 14.4.3.10/14-31 0x026 PCI Express Prefetchable Memory Limit Register (RC mode only)1 R/W 0x0000 14.4.3.
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Complete List of Configuration, Control, and Status Registers Table A-20. PCI Express Controller Registers PCI Express—Block Base Address 0x0_9000 Offset Register Access Reset Section/Page 0x070 PCI Express MSI Message Capability ID Register (EP mode only) R 0x05 14.4.4.20/14-49 0x072 PCI Express MSI Message Control Register (EP mode only) Mixed 0x0088 14.4.4.21/14-49 0x074 PCI Express MSI Message Address Register (EP mode only) R/W 0x0000_0000 14.4.4.
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Complete List of Configuration, Control, and Status Registers Table A-20. PCI Express Controller Registers PCI Express—Block Base Address 0x0_9000 Offset Register Access Reset Section/Page 0x480 PCI Express Link Capabilities Update Register (PEX_LINKCAP_UPDATE) R/W 0x0000_3D41 14.4.6.10/14-69 0x490 PCI Express Slot Capabilities Update Register (PEX_SLCAP_UPDATE) R/W 0x0000_07C0 14.4.6.11/14-71 0x4B0 PCI Express Configuration Ready Register (PEX_CFG_READY) Mixed 0x0000_0000 14.4.6.
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Complete List of Configuration, Control, and Status Registers Table A-20. PCI Express Controller Registers PCI Express—Block Base Address 0x0_9000 Offset Register Access Reset Section/Page 0x8E0 PCI Express Inbound PIO Control Register (PEX_CSB_IBCTRL) R/W 0x0000_0000 14.5.4.1/14-82 0x8E4 PCI Express Inbound PIO Status Register (PEX_CSB_IBSTAT) w1c 0x0000_0000 14.5.4.
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Complete List of Configuration, Control, and Status Registers Table A-20. PCI Express Controller Registers PCI Express—Block Base Address 0x0_9000 Offset Register Access Reset Section/Page 0xBE4 CSB System Write DMA Interrupt Enable Register (PEX_CSWDIER) R/W 0x0000_0000 14.5.8.2/14-95 0xBE8 CSB System Read DMA Interrupt Enable Register (PEX_CSRDIER) R/W 0x0000_0000 14.5.8.3/14-96 0xBEC CSB System Miscellaneous Interrupt Enable Register (PEX_CSMIER) R/W 0x0000_0002 14.5.8.
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Complete List of Configuration, Control, and Status Registers Table A-20. PCI Express Controller Registers PCI Express—Block Base Address 0x0_9000 Offset Register Access Reset Section/Page 0xCD0 PCI Express Outbound Window Attributes Register 3 (PEX_OWAR3) R/W 0x0000_0000 14.5.10.1/14-104 0xCD4 PCI Express Outbound Window Base Address Register 3 (PEX_OWBAR3) R/W 0x0000_0000 14.5.10.
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Complete List of Configuration, Control, and Status Registers Table A-20. PCI Express Controller Registers PCI Express—Block Base Address 0x0_9000 1 Offset Register Access Reset Section/Page 0xE8C PCI Express RC Inbound Window Base Address Register High 2 (PEX_RCIWBARH2) R/W 0x0000_0000 14.5.12.4/14-111 0xE90 PCI Express RC Inbound Window Attributes Register 3 (PEX_RCIWAR3) R/W 0x0000_0000 14.5.12.
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Complete List of Configuration, Control, and Status Registers Table A-21. Enhanced Three-Speed Ethernet Controllers (eTSECs) Registers (continued) eTSEC 1—Block Base Address 0x2_4000 eTSEC 2—Block Base Address 0x2_5000 eTSEC1 Offset Name1 Access 2 Reset Section/Page 0x100 TCTRL—Transmit control register R/W 0x0000_0000 16.5.3.2.1/16-34 0x104 TSTAT—Transmit status register w1c 0x0000_0000 16.5.3.2.2/16-36 0x108 DFVLAN*—Default VLAN control word R/W 0x8100_0000 16.5.3.2.
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Complete List of Configuration, Control, and Status Registers Table A-21. Enhanced Three-Speed Ethernet Controllers (eTSECs) Registers (continued) eTSEC 1—Block Base Address 0x2_4000 eTSEC 2—Block Base Address 0x2_5000 eTSEC1 Offset Name1 Access 2 Reset Section/Page R/W 0x0000_0000 16.5.3.2.9/16-45 — — — R/W 0x0000_0000 16.5.3.2.9/16-45 — — — R/W 0x0000_0000 16.5.3.2.9/16-45 — — — R/W 0x0000_0000 16.5.3.2.9/16-45 — — — R/W 0x0000_0000 16.5.3.2.
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Complete List of Configuration, Control, and Status Registers Table A-21. Enhanced Three-Speed Ethernet Controllers (eTSECs) Registers (continued) eTSEC 1—Block Base Address 0x2_4000 eTSEC 2—Block Base Address 0x2_5000 eTSEC1 Offset Name1 Access 2 Reset Section/Page 0x338 RQFCR*—Receive queue filing table control register R/W 0xnnnn_nnnn 16.5.3.3.7/16-54 0x33C RQFPR*—Receive queue filing table property register R/W 0xnnnn_nnnn 16.5.3.3.
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Complete List of Configuration, Control, and Status Registers Table A-21. Enhanced Three-Speed Ethernet Controllers (eTSECs) Registers (continued) eTSEC 1—Block Base Address 0x2_4000 eTSEC 2—Block Base Address 0x2_5000 eTSEC1 Offset Name1 Access 2 Reset Section/Page — — — R/W 0x0000_0000 16.5.3.3.11/16-60 — — — R/W 0x0000_0000 16.5.3.3.
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Complete List of Configuration, Control, and Status Registers Table A-21. Enhanced Three-Speed Ethernet Controllers (eTSECs) Registers (continued) eTSEC 1—Block Base Address 0x2_4000 eTSEC 2—Block Base Address 0x2_5000 eTSEC1 Offset Name1 Access 2 Reset Section/Page 16.5.3.5.15/16-75 16.5.3.5.
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Complete List of Configuration, Control, and Status Registers Table A-21. Enhanced Three-Speed Ethernet Controllers (eTSECs) Registers (continued) eTSEC 1—Block Base Address 0x2_4000 eTSEC 2—Block Base Address 0x2_5000 eTSEC1 Offset Name1 Access 2 Reset Section/Page 0x680 TR64—Transmit and receive 64-byte frame counter R/W 0x0000_0000 16.5.3.6.1/16-78 0x684 TR127—Transmit and receive 65- to 127-byte frame counter R/W 0x0000_0000 16.5.3.6.
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Complete List of Configuration, Control, and Status Registers Table A-21. Enhanced Three-Speed Ethernet Controllers (eTSECs) Registers (continued) eTSEC 1—Block Base Address 0x2_4000 eTSEC 2—Block Base Address 0x2_5000 eTSEC1 Offset Name1 Access 2 Reset Section/Page 0x6F8 TEDF—Transmit excessive deferral packet counter R/W 0x0000_0000 16.5.3.6.31/16-92 0x6FC TSCL—Transmit single collision packet counter R/W 0x0000_0000 16.5.3.6.
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Complete List of Configuration, Control, and Status Registers Table A-21. Enhanced Three-Speed Ethernet Controllers (eTSECs) Registers (continued) eTSEC 1—Block Base Address 0x2_4000 eTSEC 2—Block Base Address 0x2_5000 eTSEC1 Offset Name1 Access 2 Reset Section/Page 16.5.3.7.
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Complete List of Configuration, Control, and Status Registers Table A-21.
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Complete List of Configuration, Control, and Status Registers Table A-21. Enhanced Three-Speed Ethernet Controllers (eTSECs) Registers (continued) eTSEC 1—Block Base Address 0x2_4000 eTSEC 2—Block Base Address 0x2_5000 eTSEC1 Offset Name1 Access 2 Reset Section/Page 0xE80 TMR_FIPER1* - Timer fixed period interval R/W 0xFFFF_FFFF 16.5.3.10.
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Complete List of Configuration, Control, and Status Registers A.22 Enhanced Secure Digital Host Controller (eSDHC) Table A-23. Enhanced Secure Digital Host Controller (eSDHC) Registers eSDHC Registers—Block Base Address 0x2_E000 Offset Access Reset Section/Page 0x000 DMA system address (DSADDR) R/W 0x0000_0000 11.4.1/11-7 0x004 Block attributes (BLKATTR) R/W 0x0001_0000 11.4.2/11-7 0x008 Command argument (CMDARG) R/W 0x0000_0000 11.4.
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Complete List of Configuration, Control, and Status Registers Table A-24. USB Interface Registers (continued) Offset 0x100 Register CAPLENGTH—Capability register length number1 Access Reset Section/Page R 0x40 13.3.1.1/1313-6 R 0x0100 13.3.1.2/1313-7 0x102 HCIVERSION—Host interface version 0x104 HCSPARAMS—Host controller structural parameters1 R 0x0001_0011 13.3.1.3/1313-7 0x108 HCCPARAMS—Host controller capability parameters1 R 0x0000_0006 13.3.1.
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Complete List of Configuration, Control, and Status Registers Table A-24. USB Interface Registers (continued) Offset 1 Register Access Reset Section/Page 0x40C PRI_CTRL—Priority control R/W 0x0000_0000 13.3.2.26/1313-42 0x410 SI_CTRL—System interface control R/W 0x0000_0000 13.3.2.27/1313-42 0x500 CONTROL—Control R/W 0x0000_0000 13.3.2.
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Appendix B Revision History This appendix provides a list of major differences between revisions of the MPC8308 PowerQUICC II Pro Integrated Communications Processor Reference Manual. Table B-1. Changes from Revision 0 to Revision 1 Section # (Fig #/title Table#/title) Description Throughout Throughout Replaced signal name “RTC_PIT_CLK” with “RTC_PIT_CLOCK”. Throughout Changed ‘USB_CLK_IN’ to ‘USBDR_CLK’. Throughout Changed the bit name “LBIUCM” to “LBCM”.
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Revision History Table B-1. Changes from Revision 0 to Revision 1 Section # (Fig #/title Table#/title) Description Section 4.5.1.3, “Reset Status Register (RSR)” In the reset value footnote and bit description of the RSTSRC bit, updated the reset configuration input signals name to “CFG_RESET_SOURCE[0:3]”. Figure 4-7, Clock Subsystem Block Updated the figure. Diagram Table 4-23, Configurable Clock Units Removed options “csb_clk/2, csb_clk/3” from the PCIEXP unit.
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Revision History Table B-1. Changes from Revision 0 to Revision 1 Section # (Fig #/title Table#/title) Description Table 8-1, IPIC Signal Properties Added a row for the INTA signal. Table 8-2, IPIC External Signals—Detailed Signal Descriptions Added a row for the INTA signal. Figure 8-16, System External Interrupt Mask Register (SEMSR) Removed the reset value footnote saying “The user should drive...
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Revision History Table B-1. Changes from Revision 0 to Revision 1 Section # (Fig #/title Table#/title) Description Figure 12-17, TCD Word 2 Updated the TCD Word 2 fields. (TCD.{smloe, dmloe, nbytes}) Field Table 12-18, TCD Word 2 (TCD.{smloe, dmloe, nbytes}) Description Universal Serial Bus Interface Section 13.3.2.28, “USB General Purpose Register (CONTROL)—Non-EHCI” Added the CONTROL[PHY_CLK_VALID] bit.
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Revision History Table B-1. Changes from Revision 0 to Revision 1 Section # (Fig #/title Table#/title) Description Figure 19-12, Example Updated the reset value from “All zeros” to “All ones”. Also, removed "Offset 0x36".
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Revision History MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev.