Datasheet

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
Freescale Semiconductor 9
RESET Initialization
5.2 RESET AC Electrical Characteristics
This table provides the reset initialization AC timing specifications.
This table provides the PLL lock times.
Table 11. RESET Initialization Timing Specifications
Parameter/Condition Min Max Unit Notes
Required assertion time of HRESET (input) to activate reset flow 32 — t
SYS_CLK_IN
1
Required assertion time of PORESET with stable power and clock applied to
SYS_CLK_IN
32 — t
SYS_CLK_IN
—
HRESET
assertion (output) 512 — t
SYS_CLK_IN
1
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:3]) with
respect to negation of PORESET
4—t
SYS_CLK_IN
—
Input hold time for POR configuration signals with respect to negation of HRESET 0— ns —
Time for the device to turn off POR configuration signal drivers with respect to the
assertion of HRESET
—4 ns 2
Time for the device to turn on POR configuration signal drivers with respect to the
negation of HRESET
1— ns 1, 2
Notes:
1. t
SYS_CLK_IN
is the clock period of the input clock applied to SYS_CLK_IN.
2. POR configuration signals consists of CFG_RESET_SOURCE[0:3].
Table 12. PLL Lock Times
Parameter/Condition Min Max Unit Note
System PLL lock time — 100 s—
e300 core PLL lock time — 100 s—