Datasheet

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
82 Freescale Semiconductor
Document Revision History
25 Document Revision History
This table summarizes a revision history for this document.
Table 63. Document Revision History
Rev.
Number
Date Substantive Change(s)
3 10/2011 • In Section 2.1.4, “Power Sequencing,” changed description.
•In Table 53, updated GPIOs pins as I/O.
•In Table 54, removed PCI Express = csb_clk/2 and csb_clk/3 options.
•In Table 61, added note 4.
2 02/2011 • Added NV
DDJ
to Note-7 in Tabl e 1.
•In Table 2 ,
Added Note-2
Added NV
DDJ
to Note-3
Added “Extended Temperature range from -40 to 105 C, in the last row of the table
Changed “characteristic name Junction temperature” to “Operating temperature range”
•In Table 4 , Note-3, changed ambient temperature to junction temperature, T
J
= 105 C
•In Table 1 8,
t
DDKHCS
changed from 3.15ns to 2.5ns
t
DDKHMP
and t
DDKHME
values updated
•In Figure 6, corrected t
DDKHMP
& t
DDKHME
waveform
•In Table 5 3,
Y23 Package Pin Number changed from NC to V
DD
signal group
TSEC2_CRS is muxed with GPIO[0], shown as TSEC2_CRS/ GPIO[0]
•In Table 5 8, note-1, core_clk maximum operating frequency 333 MHz replaced with 400 MHz
1 06/2010 • In Table 4 , T
A
= 105 replaced with T
J
= 105
•In Tabl e 8, f
SYS_CLK_IN
(Max) = 66 replaced with 66.67 and t
SYS_CLK_IN
(Min) = 15.15 replaced with 15
•In Table 5 3, TSEC1_TMR_RX_ESFD replaced with TSEC2_TMR_RX_ESFD
TSEC1_TMR_TX_ESFD replaced with TSEC2_TMR_TX_ESFD
TSEC0_TMR_RX_ESFD replaced with TSEC1_TMR_RX_ESFD
TSEC0_TMR_TX_ESFD replaced with TSEC1_TMR_TX_ESFD
•In Table 5 6, rows from 1000 to 1111 removed
•In Table 5 7, SPMF 5:1 Option 167 MHz added.
0 05/2010 Initial release