Datasheet

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
8 Freescale Semiconductor
RESET Initialization
Table 9. RTC_PIT_CLOCK AC Timing Specifications
5 RESET Initialization
This section describes the DC and AC electrical specifications for the reset initialization timing and
electrical requirements of the device.
5.1 RESET DC Electrical Characteristics
This table provides the DC electrical characteristics for the RESET pins.
Table 8. SYS_CLK_IN AC Timing Specifications
Parameter/ Symbol Min Typ Max Unit Notes
SYS_CLK_IN frequency f
SYS_CLK_IN
24 — 66.67 MHz 1, 6
SYS_CLK_IN period t
SYS_CLK_IN
15 — 41.67 ns —
SYS_CLK_IN rise and fall time t
KH
, t
KL
0.6 1.2 ns 2
SYS_CLK_IN duty cycle t
KHK
/t
SYS_CLK_IN
40 — 60 % 3
SYS_CLK_IN jitter — — — ±150 ps 4, 5
Notes:
1. Caution: The system and core must not exceed their respective maximum or minimum operating frequencies.
2. Rise and fall times for SYS_CLK_IN are measured at 0.4 and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The SYS_CLK_IN driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to
allow cascade-connected PLL-based devices to track SYS_CLK_IN drivers with the specified jitter.
6. Spread spectrum is allowed up to 1% down-spread @ 33 kHz (max rate).
Parameter/
Symbol Min Typ Max Unit Notes
RTC_PIT_CLOCK frequency f
RTC_PIT_CLOCK
1 32768 — Hz —
RTC_PIT_CLOCK rise and fall time t
RTCH
, t
RTCL
1.5 — 3 s—
RTC_PIT_CLOCK duty cycle t
RTCHK
/t
RTC_PIT_CLO
CK
45 — 55 % —
Table 10. RESET Pins DC Electrical Characteristics
Characteristic Symbol Condition Min Max Unit
Input high voltage V
IH
—2.0NV
DD
+0.3 V
Input low voltage V
IL
—–0.30.8V
Input current I
IN
0 V  V
IN
NV
DD
±5 A
Output high voltage V
OH
I
OH
= –8.0 mA 2.4 — V
Output low voltage V
OL
I
OL
= 8.0 mA — 0.5 V
Output low voltage V
OL
I
OL
= 3.2 mA — 0.4 V