Datasheet

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
78 Freescale Semiconductor
System Design Information
23.3 Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the device can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the MPC8308 system, and the MPC8308
itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system
designer place at least one decoupling capacitor at each V
DD
, NV
DD
, GV
DD
and LV
DD
pin of the device.
These decoupling capacitors should receive their power from separate V
DD
, NV
DD
, GV
DD
, LV
DD
, and
V
SS
power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed
directly under the device using a standard escape pattern. Others may surround the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the V
DD
, NV
DD
, GV
DD
, LV
DD
planes, to enable quick recharging of the smaller chip capacitors.
These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick
response time necessary. They should also be connected to the power and ground planes through two vias
to minimize inductance. Suggested bulk capacitors—100 to 330 µF (AVX TPS tantalum or Sanyo
OSCON). However, customers should work directly with their power regulator vendor for best values and
types of bulk capacitors.
23.4 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to NV
DD
, GV
DD
, LV
DD
as required. Unused active high
inputs should be connected to VSS. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external V
DD
, NV
DD
, AV
DD1
, AV
DD2
, GV
DD
, LV
DD
and V
SS
pins of the device.
23.5 Output Buffer DC Impedance
The device drivers are characterized over process, voltage, and temperature. For all buses, the driver is a
push-pull single-ended driver type (open drain for I
2
C, MDIO and HRESET)
To measure Z
0
for the single-ended drivers, an external resistor is connected from the chip pad to NV
DD
or V
SS
. Then, the value of each resistor is varied until the pad voltage is NV
DD
/2 (Figure 55). The output
impedance is the average of two components, the resistances of the pull-up and pull-down devices. When
data is held high, SW1 is closed (SW2 is open), and R
P
is trimmed until the voltage at the pad equals
NV
DD
/2. R
P
then becomes the resistance of the pull-up devices. R
P
and R
N
are designed to be close to each
other in value. Then, Z
0
= (R
P
+ R
N
)/2.