Datasheet

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
Freescale Semiconductor 77
System Design Information
23 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
device
23.1 System Clocking
The device includes two PLLs.
1. The platform PLL generates the platform clock from the externally supplied SYS_CLK_IN input.
The frequency ratio between the platform and SYS_CLK_IN is selected using the platform PLL
ratio configuration bits as described in Section 21.2, “System PLL Configuration.”
2. The e300 core PLL generates the core clock as a slave to the platform clock. The frequency ratio
between the e300 core clock and the platform clock is selected using the e300 PLL ratio
configuration bits as described in Section 21.3, “Core PLL Configuration.”
23.2 PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins (AV
DD1
for
core PLL and AV
DD2
for the platform PLL). The AV
DD
level should always be equivalent to V
DD
, and
preferably these voltages are derived directly from V
DD
through a low pass filter scheme such as the
following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide independent filter circuits as illustrated in Figure 54, one to each of the two AV
DD
pins. By
providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs’ resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum effective series inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AV
DD
pin being supplied to minimize
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV
DD
pin, which is on the periphery of package, without the inductance of vias.
This figure shows the PLL power supply filter circuits.
Figure 54. PLL Power Supply Filter Circuit
V
DD
AV
DD1
and AV
DD2
2.2 µF 2.2 µF
Low ESL Surface Mount Capacitors
10