Datasheet

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
Freescale Semiconductor 73
Clocking
This table provides the operating frequencies for the device under recommended operating conditions
(Table 2).
21.2 System PLL Configuration
The system PLL is controlled by the RCWL[SPMF] parameter. This table shows the multiplication factor
encodings for the system PLL.
As described in Section 21, “Clocking,” the LBCM, DDRCM, and SPMF parameters in the reset
configuration word low select the ratio between the primary clock input (SYS_CLK_IN) and the internal
coherent system bus clock (csb_clk). This table shows the expected frequency values for the CSB
frequency for select csb_clk to SYS_CLK_IN ratios.
Table 55. Operating Frequencies for MPC8308
Characteristic
1
Maximum Operating Frequency Unit
e300 core frequency (core_clk) 400 MHz
Coherent system bus frequency (csb_clk) 133 MHz
DDR2 memory bus frequency (MCK)
2
133 MHz
Local bus frequency (LCLK0)
3
66 MHz
Notes:
1. The SYS_CLK_IN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting csb_clk,
MCK, LCLK0, and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies.
2. The DDR data rate is 2x the DDR memory bus frequency.
3. The local bus frequency is 1/2, 1/4, or 1/8 of the lbc_clk frequency (depending on LCCR[CLKDIV]) which is in turn, 1x or 2x
the csb_clk frequency (depending on RCWL[LBCM]).
Table 56. System PLL Ratio
RCWL[SPMF] csb_clk: SYS_CLK_IN
0000 Reserved
0001 Reserved
0010 2 : 1
0011 3 : 1
0100 4 : 1
0101 5 : 1
0110–1111 Reserved
Table 57. CSB Frequency Options
SPMF
csb_clk :Input Clock Ratio
Input Clock Frequency (MHz)
25 33.33 66.67
0010 2:1
133
0100 4:1 133
0101 5:1 125 167