Datasheet

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3

72 Freescale Semiconductor

Clocking

21.1 System Clock Domains

The primary clock input (SYS_CLK_IN) frequency is multiplied up by the system phase-locked loop

(PLL) and the clock unit to create three major clock domains:

• The coherent system bus clock (csb_clk)

• The internal clock for the DDR controller (ddr_clk)

• The internal clock for the local bus interface unit (lbc_clk)

The csb_clk frequency is derived as follows:

csb_clk = [SYS_CLK_IN] × SPMF

The csb_clk serves as the clock input to the e300 core. A second PLL inside the core multiplies up the

csb_clk frequency to create the internal clock for the core (core_clk). The system and core PLL multipliers

are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL), which is

loaded at power-on reset or by one of the hard-coded reset options. For more information, see the Reset

Clock Configuration chapter in the MPC8308 PowerQUICC II Pro Processor Reference Manual.

The DDR SDRAM memory controller will operate with a frequency equal to twice the frequency of

csb_clk. Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR

clock divider (2) to create the differential DDR memory bus clock outputs (MCK and MCK). However,

the data rate is the same frequency as ddr_clk.

The local bus memory controller will operate with a frequency equal to the frequency of csb_clk. Note that

lbc_clk is not the external local bus frequency; lbc_clk passes through the LBC clock divider to create the

external local bus clock outputs (LSYNC_OUT and LCLK0:2). The LBC clock divider ratio is controlled

by LCCR[CLKDIV]. For more information, see the Reset Clock Configuration chapter in the MPC8308

PowerQUICC II Pro Processor Reference Manual.

In addition, some of the internal units may be required to be shut off or operate at lower frequency than

the csb_clk frequency. These units have a default clock ratio that can be configured by a memory mapped

frequency. For more information, see Reset Clock Configuration chapter in the MPC8308 PowerQUICC

II Pro Processor Reference Manual.

NOTE

The clock ratios of these units must be set before they are accessed.

Table 54. Configurable Clock Units

Unit Default Frequency Options

eTSEC1,eTSEC2 csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3

C csb_clk Off, csb_clk,csb_clk/2, csb_clk/3

DMA complex csb_clk Off, csb_clk,csb_clk/2,csb_clk/3

PCIEXP csb_clk Off, csb_clk

eSDHC csb_clk Off, csb_clk, csb_clk/2, csb_clk/3

USB csb_clk Off, csb_clk, csb_clk/2, csb_clk/3