Datasheet

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
Freescale Semiconductor 71
Clocking
21 Clocking
This figure shows the internal distribution of clocks within the device.
1
Multiplication factor M = 1, 1.5, 2, 2.5, and 3. Value is decided by RCWLR[COREPLL].
2
Multiplication factor L = 2, 3, 4, 5 and 6. Value is decided by RCWLR[SPMF].
Figure 53. MPC8308 Clock Subsystem
The following external clock sources are utilized on the MPC8308:
• System clock (SYS_CLK_IN)
• Ethernet Clock (TSEC1_RX_CLK/TSEC1_TX_CLK/TSEC1_GTX_CLK125 for eTSEC)
• SerDes PHY clock
• eSHDC clock (SD_CLK)
For more information, see the SerDes chapter in the MPC8308 PowerQUICC II Pro Processor
Reference Manual.
All clock inputs can be supplied using an external canned oscillator, a clock generation chip, or some other
source that provides a standard CMOS square wave input.
PCI Express
e300 Core
System
PLL
e300
PLL
Clk
Gen
125/100 MHz
PLL
fbref
SYS_CLK_IN
PCVTR Mux
Protocol
Converter
SerDes PHY
+
-
24–66 MHz
SD_REF_CLK_B
SD_REF_CLK
MPC8308
eTSEC1
TSEC1_RX_CLK
TSEC1_TX_CLK/
TSEC1_GTX_CLK125
DDR
Clock
/2
Divider
/n
csb_clk
LBC
Clock
Divider
clk tree
MCK[0:2]
MCK
[0:2]
DDR
Memory
Device
Local
Bus
Memory
Device
ddr_clk
lbc_clk
x M
1
x L
2
eSHDC
SD_CLK