Datasheet

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
Freescale Semiconductor 59
Package and Pin Listings
This figure shows the SPI timing in slave mode (external clock).
Figure 50. SPI AC Timing in Slave Mode (External Clock) Diagram
This figure shows the SPI timing in master mode (internal clock).
Figure 51. SPI AC Timing in Master Mode (Internal Clock) Diagram
20 Package and Pin Listings
This section details package parameters, pin assignments, and dimensions. The MPC8308 is available in
a moulded array process ball grid array (MAPBGA). For information on the MAPBGA, see Section 20.1,
“Package Parameters for the MPC8308 MAPBGA,” and Section 20.2, “Mechanical Dimensions of the
MPC8308 MAPBGA.”
20.1 Package Parameters for the MPC8308 MAPBGA
The package parameters are as provided in the following list. The package type is 19 mm  19 mm, 473
MAPBGA.
Package outline 19 mm 19 mm
Interconnects 473
Pitch 0.80 mm
Module height (typical) 1.39 mm
Solder Balls 96.5 Sn/ 3.5Ag
Ball diameter (typical) 0.40 mm
SPICLK (input)
t
NEIXKH
t
NEIVKH
t
NEKHOV
Input Signals:
SPIMOSI
(See Note)
Output Signals:
SPIMISO
(See Note)
Note: The clock edge is selectable on SPI.
SPICLK (output)
t
NIIXKH
t
NIKHOV
Input Signals:
SPIMISO
(See Note)
Output Signals:
SPIMOSI
(See Note)
Note: The clock edge is selectable on SPI.
t
NIIVKH