Datasheet

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
Freescale Semiconductor 53
I
2
C
15 I
2
C
This section describes the DC and AC electrical characteristics for the I
2
C interface.
15.1 I
2
C DC Electrical Characteristics
This table provides the DC electrical characteristics for the I
2
C interface.
15.2 I
2
C AC Electrical Specifications
This table provides the AC timing parameters for the I
2
C interface.
Table 43. I
2
C DC Electrical Characteristics
At recommended operating conditions with NV
DD
of 3.3 V ± 0.3 V.
Parameter Symbol Min Max Unit Notes
Input high voltage level V
IH
0.7  NV
DD
NV
DD
+ 0.3 V —
Input low voltage level V
IL
–0.3 0.3  NV
DD
V—
Low level output voltage V
OL
00.2  NV
DD
V1
High level output voltage V
OH
0.8 x NV
DD
NV
DD
+ 0.3 V —
Output fall time from V
IH
(min) to V
IL
(max) with a bus capacitance from 10
to 400 pF
t
I2KLKV
20 + 0.1  C
B
250 ns 2
Pulse width of spikes which must be suppressed by the input filter t
I2KHKL
050ns3
Capacitance for each I/O pin C
I
—10pF—
Input current, (0 V V
IN
NV
DD
)I
IN
—± 5 A—
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. C
B
= capacitance of one bus line in pF.
3. For information on the digital filter used, see the MPC8308 PowerQUICC II Pro Processor Reference Manual.
Table 44. I
2
C AC Electrical Specifications
All values refer to V
IH
(min) and V
IL
(max) levels (see Ta bl e 4 3).
Parameter Symbol
1
Min Max Unit
SCL clock frequency f
I2C
0 400 kHz
Low period of the SCL clock t
I2CL
1.3 — s
High period of the SCL clock t
I2CH
0.6 — s
Setup time for a repeated START condition t
I2SVKH
0.6 — s
Hold time (repeated) START condition (after this period, the first clock pulse is generated) t
I2SXKL
0.6 — s
Data setup time t
I2DVKH
100 — ns
Data hold time:
I
2
C bus devices
t
I2DXKL
—
0
2
—
0.9
3
s
Fall time of both SDA and SCL signals
5
t
I2CF
—300ns