Datasheet

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
52 Freescale Semiconductor
JTAG
This figure provides the TRST timing diagram.
Figure 42. TRST Timing Diagram
This figure provides the boundary-scan timing diagram.
Figure 43. Boundary-Scan Timing Diagram
This figure provides the test access port timing diagram.
Figure 44. Test Access Port Timing Diagram
TRST
VM = Midpoint Voltage (NV
DD
/2)
VM VM
t
TRST
VM = Midpoint Voltage (NV
DD
/2)
VM VM
t
JTDVKH
t
JTDXKH
Boundary
Data Outputs
Boundary
Data Outputs
JTAG
External Clock
Boundary
Data Inputs
Output Data Valid
t
JTKLDX
t
JTKLDZ
t
JTKLDV
Input
Data Valid
Output Data Valid
VM = Midpoint Voltage (NV
DD
/2)
VM VM
t
JTIVKH
t
JTIXKH
JTAG
External Clock
Output Data Valid
t
JTKLOX
t
JTKLOZ
t
JTKLOV
Input
Data Valid
Output Data Valid
TDI, TMS
TDO
TDO