Datasheet

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
Freescale Semiconductor 5
Electrical Characteristics
This figure shows the undershoot and overshoot voltages at the interfaces of the device.
Figure 2. Overshoot/Undershoot Voltage for GVDD/NVDD/LVDD
2.1.3 Output Driver Characteristics
This table provides information on the characteristics of the output driver strengths.
2.1.4 Power Sequencing
It is required to apply the core supply voltage (V
DD
) before the I/O supply voltages (GV
DD
, LV
DD
, and
NV
DD
) and assert PORESET before the power supplies fully ramp up. The core voltage supply must rise
to 90% of its nominal value before the I/O supplies reach 0.7 V; see Figure 3.
If this recommendation is not observed and I/O voltages are supplied before the core voltage, there might
be a period of time that all input and output pins are actively driven and cause contention and excessive
current. To overcome side effects of this condition, the application environment may require tuning of
external pull-up or pull-down resistors on particular signals to lesser values.
Table 3. Output Drive Capability
Driver Type Output Impedance () Supply Voltage
Local bus interface utilities signals 42 NV
DD
= 3.3 V
DDR2 signals
1
1
Output Impedance can also be adjusted through configurable options in DDR Control Driver Register (DDRCDR).
For more information, see the MPC8308 PowerQUICC II Pro Processor Reference Manual.
18 GV
DD
= 1.8 V
DUART, system control, I
2
C, JTAG, eSDHC, GPIO,SPI, USB 42 NV
DD
= 3.3 V
eTSEC signals 42 LV
DD
= 2.5/3.3 V
VSS
VSS – 0.3 V
VSS – 0.7 V
Not to Exceed 10%
G/L/NV
DD
+ 20%
G/L/NV
DD
G/L/NV
DD
+ 5%
of t
interface
1
1. t
interface
refers to the clock period associated with the bus clock interface.
V
IH
V
IL
Note: