Datasheet

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
Freescale Semiconductor 49
Enhanced Secure Digital Host Controller (eSDHC)
13.3.1 High Speed Output Path (Write)
This figure provides the data and command output timing diagram.
Figure 38. High Speed Output Path
13.3.2 High Speed Input Path (Read)
This figure provides the data and command input timing diagram.
Figure 39. High Speed Input Path
Output Valid Time: t
SHSKHOV
Output Hold Time: t
SHSKHOX
t
IH
(2 ns)
t
CLK_DELAY
Input at the
SD CLK at
Driving
Edge
Sampling
Edge
the Card Pin
SD Card Pins
t
ISU
(6 ns)
t
DATA_DELAY
t
SHSCKL
t
SHSCK
(Clock Cycle)
SD CLK at the
MPC8308 Pin
Output from the
MPC8308 Pins
t
CLK_DELAY
Output from the
SD CLK at
the Card Pin
SD Card Pins
t
SHSIVKH
Driving
Edge
Sampling
Edge
t
OH
t
DATA_DELAY
t
ODLY
t
SHSCK
(Clock Cycle)
1/2 Cycle
t
SHSIXKH
(MPC8308 Input
(MPC8308 Input
Input at the
MPC8308 Pins
SD CLK at the
MPC8308 Pin