Datasheet

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
48 Freescale Semiconductor
Enhanced Secure Digital Host Controller (eSDHC)
This figure provides the eSDHC clock input timing diagram.
Figure 37. eSDHC Clock Input Timing Diagram
SD Card Output Valid t
ODLY
—14ns3
SD Card Output Hold t
OH
2.5 — ns 3
Notes:
1
The symbols used for timing specifications herein follow the pattern of t
(first three letters of functional block)(signal)(state) (reference)(state)
for inputs and t
(first three letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
SFSIXKH
symbolizes eSDHC
full mode speed device timing (SFS) input (I) to go invalid (X) with respect to the clock reference (K) going to high (H). Also
t
SFSKHOV
symbolizes eSDHC full speed timing (SFS) for the clock reference (K) to go high (H), with respect to the output (O)
going valid (V) or data output valid time. Note that, in general, the clock reference symbol representation is based on five
letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
2
Measured at capacitive load of 40 pF.
3
For reference only, according to the SD card specifications.
Table 40. eSDHC AC Timing Specifications for High Speed Mode (continued)
At recommended operating conditions NV
DD
= 3.3 V ± 300 mV.
Parameter Symbol
1
Min Max Unit Notes
eSDHC
t
SHSCKR
External Clock
VMVMVM
t
SHSCK
t
SHSCKF
VM = Midpoint Voltage (NVDD/2)
operational mode
t
SHSCK
L
t
SHSCKH