Datasheet

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
Freescale Semiconductor 47
Enhanced Secure Digital Host Controller (eSDHC)
13.2.2 Full Speed Input Path (Read)
This figure provides the data and command input timing diagram.
Figure 36. Full Speed Input Path
13.3 eSDHC AC Timing Specifications
This table provides the eSDHC AC timing specifications.
Table 40. eSDHC AC Timing Specifications for High Speed Mode
At recommended operating conditions NV
DD
= 3.3 V ± 300 mV.
Parameter Symbol
1
Min Max Unit Notes
SD_CLK clock frequency—high speed mode f
SHSCK
050MHz3
SD_CLK clock cycle t
SHSCK
20 — ns —
SD_CLK clock frequency—identification mode f
SIDCK
0400kHz—
SD_CLK clock low time t
SHSCKL
7—ns2
SD_CLK clock high time t
SHSCKH
7—ns2
SD_CLK clock rise and fall times t
SHSCKR/
t
SHSCKF
—3ns2
Input setup times: SD_CMD, SD_DATx t
SHSIVKH
3—ns2
Input hold times: SD_CMD, SD_DATx t
SHSIXKH
2—ns2
Output delay time: SD_CLK to SD_CMD, SD_DATx valid t
SHSKHOV
3—ns2
Output Hold time: SD_CLK to SD_CMD, SD_DATx invalid t
SHSKHOX
–3 — ns 2
SD Card Input Setup t
ISU
6—ns3
SD Card Input Hold t
IH
2—ns3
t
CLK_DELAY
Output from the
SD CLK at
the Card Pin
SD Card Pins
t
SFSIVKH
t
SFSIXKH
Driving
Edge
Sampling
Edge
t
OH
t
DATA_DELAY
t
ODLY
t
SFSCK
(Clock Cycle)
(MPC8308 Input Hold)
SD CLK at the
MPC8308 Pin
Input at the
MPC8308 Pins