Datasheet

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
46 Freescale Semiconductor
Enhanced Secure Digital Host Controller (eSDHC)
This figure provides the eSDHC clock input timing diagram.
Figure 34. eSDHC Clock Input Timing Diagram
13.2.1 Full Speed Output Path (Write)
This figure provides the data and command output timing diagram.
Figure 35. Full Speed Output Path
eSDHC
t
SFSCKR
External Clock
VMVMVM
t
SFSCK
t
SFSCKF
VM = Midpoint Voltage (NV
DD
/2)
operational mode
t
SFSCKL
t
SFSCKH
Input at the
MPC8308 Pins
SD CLK at the
MPC8308 Pin
Output Valid Time: t
SFSKHOV
Output Hold Time: t
SFSKHOX
t
IH
(5 ns)
t
CLK_DELAY
SD CLK at
Driving
Edge
Sampling
Edge
the Card Pin
t
ISU
(5 ns)
t
DATA_DELAY
t
SFSCKL
t
SFSCK
(Clock Cycle)
Output from the
MPC8308 Pins