Datasheet

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
44 Freescale Semiconductor
Enhanced Secure Digital Host Controller (eSDHC)
Figure 33. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4
13 Enhanced Secure Digital Host Controller (eSDHC)
This section describes the DC and AC electrical specifications for the eSDHC (SD/MMC/SDIO) interface
of the MPC8308.
The eSDHC controller always uses the falling edge of the SD_CLK in order to drive the
SD_DAT[0:3]/CMD as outputs and rising edge to sample the SD_DAT[0:3], CMD, CD and WP as inputs.
This behavior is true for both full and high speed modes.
13.1 eSDHC DC Electrical Characteristics
This table provides the DC electrical characteristics for the eSDHC (SD/MMC) interface of the device,
compatible with SDHC specifications. The eSDHC NV
DD
range is between 3.0 V and 3.6 V.
Table 38. eSDHC interface DC Electrical Characteristics
Characteristic Symbol Condition Min Max Unit
Output high voltage V
OH
I
OH
= –8.0 mA 2.4 — V
Output low voltage V
OL
I
OL
= 8.0 mA — 0.5 V
LCLK
UPM Mode Input Signal:
LUPWAIT
t
LBIXKH
t
LBIVKH
t
LBIVKH
t
LBIXKH
t
LBKHOZ
T1
T3
UPM Mode Output Signals:
LCS
[0:3]/LBS[0:1]/LGPL[0:5]
GPCM Mode Output Signals:
LCS
[0:3]/LWE
t
LBKHOV
t
LBKHOV
t
LBKHOZ
T2
T4
Input Signals:
LD[0:15]