Datasheet

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
42 Freescale Semiconductor
Enhanced Local Bus
12.1 Enhanced Local Bus DC Electrical Characteristics
This table provides the DC electrical characteristics for the local bus interface.
12.2 Enhanced Local Bus AC Electrical Specifications
This table describes the general timing parameters of the local bus interface.
This figure provides the AC test load for the local bus.
Figure 30. Local Bus AC Test Load
Table 36. Local Bus DC Electrical Characteristics at 3.3 V
Parameter Symbol Min Max Unit
High-level input voltage V
IH
2.0 NV
DD
+ 0.3 V
Low-level input voltage V
IL
–0.3 0.8 V
Input current, (V
IN
1
= 0 V or V
IN
= LV
DD
)I
IN
— ±5A
High-level output voltage, (LV
DD
= min, I
OH
= –2 mA) V
OH
NV
DD
– 0.2 — V
Low-level output voltage, (LV
DD
= min, I
OH
= 2 mA) V
OL
—0.2V
Note: The parameters stated in above table are valid for all revisions unless explicitly mentioned.
Table 37. Local Bus General Timing Parameters
Parameter Symbol
1
Min Max Unit Notes
Local bus cycle time t
LBK
15 — ns 2
Input setup to local bus clock t
LBIVKH
7 — ns 3, 4
Input hold from local bus clock t
LBIXKH
1 — ns 3, 4
Local bus clock to output valid t
LBKHOV
—3 ns 3
Local bus clock to output high impedance for LD t
LBKHOZ
—4 ns 5
Notes:
1. The symbols used for timing specifications follow the pattern of t
(First two letters of functional block)(signal)(state) (reference)(state)
for
inputs and t
(First two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
LBIXKH1
symbolizes local bus
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
LBK
clock reference (K) goes high (H), in this case
for clock one(1).
2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA
and LUPWAIT inputs) or rising edge of
LCLK0 (for all other inputs).
3. All signals are measured from NV
DD
/2 of the rising/falling edge of LCLK0 to 0.4  NV
DD
of the signal in question for 3.3-V
signaling levels.
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
Output
Z
0
= 50 
NV
DD
/2
R
L
= 50 