Datasheet

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
Freescale Semiconductor 33
High-Speed Serial Interfaces (HSSI)
Figure 24. Differential Measurement Points for Rise and Fall Time
Figure 25. Single-Ended Measurement Points for Rise and Fall Time Matching
The other detailed AC requirements of the SerDes reference clocks is defined by each interface protocol
based on application usage. For detailed information, see the following sections:
• Section 11.2, “AC Requirements for PCI Express SerDes Clocks”
Rising edge rate (SD_REF_CLK) to falling edge rate
(SD_REF_CLK) matching
Rise-Fall
Matching
—20%1, 4
Notes:
1. Measurement taken from single ended waveform.
2. Measurement taken from differential waveform.
3. Measured from –200 mV to +200 mV on the differential waveform (derived from SD_REF_CLK minus SD_REF_CLK
). The
signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered
on the differential zero crossing (Figure 24).
4. Matching applies to rising edge rate for SD_REF_CLK and falling edge rate for SD_REF_CLK
. It is measured using a 200
mV window centered on the median cross point where SD_REF_CLK rising meets SD_REF_CLK falling. The median cross
point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate
of SD_REF_CLK should be compared to the Fall Edge Rate of SD_REF_CLK
, the maximum allowed difference should not
exceed 20% of the slowest edge rate (See Figure 25).
Table 32. SerDes Reference Clock AC Parameters (continued)
At recommended operating conditions with XCOREVDD= 1.0V ± 5%
Parameter Symbol Min Max Unit Notes
V
IH
= +200
V
IL
= -200 mV
0.0 V
SD_REF_CLK
minus
SD_REF_CLK
SD_REF_CLK
SD_REF_CLK
SD_REF_CLK
SD_REF_CLK